公开(公告)号：US07572727B1

公开(公告)日：2009-08-11

申请号：US10934828

申请日：2004-09-02

申请人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

发明人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

摘要翻译： 本发明是一种半导体接触形成系统和方法。 接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。 该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。 通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。 导电材料（例如，钨）沉积在接触区域中。

公开(公告)号：US07977797B2

公开(公告)日：2011-07-12

申请号：US12539480

申请日：2009-08-11

申请人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

发明人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

IPC分类号： H01L23/522

CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

摘要翻译： 本发明是一种半导体接触形成系统和方法。 接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。 该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。 通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。 导电材料（例如，钨）沉积在接触区域中。

公开(公告)号：US07361587B1

公开(公告)日：2008-04-22

申请号：US10934923

申请日：2004-09-02

申请人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

发明人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  Y10S438/97

摘要： The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region width are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

摘要翻译： 本发明是形成接触绝缘区域的半导体接触形成系统和方法，该接触绝缘区域包括有助于形成接触的多个蚀刻停止子层。 该契约形成过程提供相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，多次蚀刻停止触点形成工艺，其中沉积包括多个蚀刻停止层的多重蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除靠近金属层，并且较小的部分被移除到靠近基板的位置。 不同的接触区域宽度通过执行由多个蚀刻停止绝缘层中的多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现。 导电材料（例如，钨）沉积在接触区域中。

公开(公告)号：US06867063B1

公开(公告)日：2005-03-15

申请号：US10262221

申请日：2002-09-30

申请人： Kouros Ghandehari ,  Dawn Hopper ,  Wenmei Li ,  Angela T. Hui

发明人： Kouros Ghandehari ,  Dawn Hopper ,  Wenmei Li ,  Angela T. Hui

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/02

CPC分类号： G03F7/091 ,  H01L21/0276

摘要： A method of manufacturing a semiconductor. A conventional bottom anti-reflective coating is applied over a reflective surface, for example an inter-layer dielectric. A second anti-reflective coating is deposited over the first anti-reflective coating. The second anti-reflective coating is organic and may be deposited through a spin-on process. The organic anti-reflective coating may be deposited with more exacting optical properties and better control of the layer thickness than conventional bottom anti-reflective coatings applied via chemical vapor deposition processes. The combination of the two layers of anti-reflective materials, the materials having differing optical properties, demonstrates superior control of reflections from underlying materials compared with conventional art methods. More particularly, an organic anti-reflective coating in conjunction with an inorganic anti-reflective coating may cancel reflections across a wide range of thicknesses in an underlying dielectric layer. The superior anti-reflective structure of embodiments of the present invention allow patterning of semiconductor structures at smaller critical dimensions with greater accuracy, rendering competitive advantages in device speed, density and cost.

摘要翻译： 一种制造半导体的方法。 常规的底部抗反射涂层施加在反射表面上，例如层间电介质。 在第一抗反射涂层上沉积第二抗反射涂层。 第二种抗反射涂层是有机的，可通过旋涂工艺沉积。 与通过化学气相沉积工艺施加的常规底部抗反射涂层相比，有机抗反射涂层可以沉积更加严格的光学性能和更好的层厚度控制。 与传统技术方法相比，两层抗反射材料（具有不同光学性质的材料）的组合表现出对来自下层材料的反射的优异控制。 更具体地，结合无机抗反射涂层的有机抗反射涂层可以消除底层电介质层中宽范围的厚度的反射。 本发明的实施例的优异的抗反射结构允许以较小的临界尺寸更精确地图案化半导体结构，从而在装置速度，密度和成本方面具有竞争优势。

公开(公告)号：US06528398B1

公开(公告)日：2003-03-04

申请号：US09775084

申请日：2001-02-01

申请人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

发明人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

IPC分类号： H01L2176

CPC分类号： G03F7/094 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76816

摘要： An exemplary embodiment described in the disclosure relates to a method of fabricating an integrated circuit which includes providing a bulk layer over a semiconductor substrate, providing an imaging layer over the bulk layer, imaging the imaging layer to expose portions of the imaging layer, removing the exposed portions of the imaging layer, etching the bulk layer at locations where exposed portions of the imaging layer were removed to provide at least one aperture in the bulk layer, and silylating the bulk layer.

摘要翻译： 本公开中描述的示例性实施例涉及一种制造集成电路的方法，其包括在半导体衬底上提供体层，在体层上提供成像层，使成像层成像以暴露成像层的部分，去除 成像层的暴露部分，在去除成像层的暴露部分的位置处蚀刻体层以在本体层中提供至少一个孔，以及使体层甲硅烷化。

公开(公告)号：US06653190B1

公开(公告)日：2003-11-25

申请号：US10023436

申请日：2001-12-15

申请人： Jean Y. Yang ,  Kouros Ghandehari ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Dawn M. Hopper ,  Angela T. Hui ,  Scott A. Bell

发明人： Jean Y. Yang ,  Kouros Ghandehari ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Dawn M. Hopper ,  Angela T. Hui ,  Scott A. Bell

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.

摘要翻译： 用于MirrorBit（闪存）闪存的制造方法包括在半导体衬底上沉积电荷捕获材料并在半导体衬底中注入第一和第二位线。 字线材料沉积在电荷俘获电介质材料上并沉积在其上的硬掩模材料。 将抗反射涂层（ARC）材料沉积在硬掩模材料上，并且将光致抗蚀剂材料沉积在ARC上，随后处理光致抗蚀剂材料和ARC材料以形成图案化光致抗蚀剂和图案化ARC的光掩模。 使用光掩模处理硬掩模材料以形成硬掩模。 去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏硬掩模或字线材料。 使用硬掩模处理字线材料以形成字线，并且去除硬掩模而不损坏字线或电荷捕获材料。

公开(公告)号：US06501555B1

公开(公告)日：2002-12-31

申请号：US09773954

申请日：2001-02-01

申请人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

发明人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

IPC分类号： G01B1128

CPC分类号： H01L22/26 ,  H01L22/12

摘要： The disclosure describes an exemplary method of detecting a process end point during etching in the fabrication of an integrated circuit. This method can include receiving a reference signal indicative of an intensity of a light source, collecting a reflection signal reflected off a surface of an integrated circuit wafer, and comparing the reference signal and the reflection signal to locate absorption bands, the absorption band being indicative of a process end point.

摘要翻译： 本公开描述了在集成电路的制造中在蚀刻期间检测处理终点的示例性方法。 该方法可以包括接收指示光源强度的参考信号，收集从集成电路晶片的表面反射的反射信号，以及比较参考信号和反射信号以定位吸收带，吸收带指示 的过程终点。

公开(公告)号：US06475867B1

公开(公告)日：2002-11-05

申请号：US09824416

申请日：2001-04-02

申请人： Angela T. Hui ,  Kouros Ghandehari ,  Bhanwar Singh

发明人： Angela T. Hui ,  Kouros Ghandehari ,  Bhanwar Singh

IPC分类号： H07L21336

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338

摘要： An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second layer of material; etching the first layer of material according to the photoresist pattern to form material features; oxidizing exposed portions of the material features where the material features are made of a material which expands during oxidation; and etching the second layer of material according to the material features which have expanded as a result of oxidation. Advantageously, the expansion of the material features results in a smaller distance between material features than the distance between photoresist features.

摘要翻译： 描述了通过钛硬掩模的氧化形成集成电路器件特征的示例性方法。 该方法可以包括在沉积在第二材料层上的第一材料层上提供光致抗蚀剂特征的光致抗蚀剂图案; 根据光致抗蚀剂图案蚀刻第一层材料以形成材料特征; 氧化材料特征的暴露部分，其中材料特征由在氧化期间膨胀的材料制成; 并根据由于氧化而膨胀的材料特征蚀刻第二层材料。 有利地，材料特征的扩展导致材料特征之间的距离比光致抗蚀剂特征之间的距离更小。

公开(公告)号：US06969654B1

公开(公告)日：2005-11-29

申请号：US09727714

申请日：2000-11-28

申请人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Angela T. Hui ,  Dawn Hopper

发明人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Angela T. Hui ,  Dawn Hopper

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L23/552 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L23/552 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.

摘要翻译： 一种在制造期间防止闪存NVROM单元的紫外线充电的方法和由此形成的装置。 在器件制造期间，在阻挡层上沉积UV阻挡层。 UV阻挡层基本上阻止UV进入栅极区域，以便防止电子迁移率足以使电池不可编程或不可擦除。 在NVROM处理期间减少的电子迁移导致器件的产量和可靠性的提高。

公开(公告)号：US08367493B1

公开(公告)日：2013-02-05

申请号：US11109719

申请日：2005-04-20

申请人： Minh Van Ngo ,  Hirokazu Tokuno ,  Angela T. Hui ,  Wenmei Li ,  Hsiao-Han Thio

发明人： Minh Van Ngo ,  Hirokazu Tokuno ,  Angela T. Hui ,  Wenmei Li ,  Hsiao-Han Thio

IPC分类号： H01L21/8238

CPC分类号： H01L23/291 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/11521 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

摘要翻译： 一种制造非易失性存储器件的方法包括形成多个存储单元。 该方法还包括在存储器单元上沉积第一介电层，其中第一介电层是具有基本均匀厚度的共形层。 该方法还包括在第一介电层上沉积第二电介质层。 第一和第二电介质层一起形成没有空隙的层间电介质。