公开(公告)号：US20060231528A1

公开(公告)日：2006-10-19

申请号：US11455023

申请日：2006-06-15

申请人： Werner Juengling ,  Steven McDonald ,  Kunal Parekh

发明人： Werner Juengling ,  Steven McDonald ,  Kunal Parekh

IPC分类号： B44C1/22 ,  C23F1/00 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

公开(公告)号：US20050255701A1

公开(公告)日：2005-11-17

申请号：US10848247

申请日：2004-05-17

申请人： Werner Juengling ,  Steven McDonald ,  Kunal Parekh

发明人： Werner Juengling ,  Steven McDonald ,  Kunal Parekh

IPC分类号： H01L21/302 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

摘要翻译： 本发明包括一种方法，通过该方法制造半导体结构的保险丝盒以在其中延伸的保险丝上具有基本均匀的层。 在具体方面，本发明包括这样的方法，其中与保险丝盒区域同时进行与接合焊盘和再分配层的制造和图案相关联的一个或多个处理步骤，以形成和/或去除直接位于保险丝盒区域上方的材料。

公开(公告)号：US20090315154A1

公开(公告)日：2009-12-24

申请号：US12142251

申请日：2008-06-19

申请人： Kyle Kirby ,  Kunal Parekh

发明人： Kyle Kirby ,  Kunal Parekh

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

摘要翻译： 描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。 金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。 制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部 金属填充通孔的区域。

公开(公告)号：US07601591B2

公开(公告)日：2009-10-13

申请号：US12020752

申请日：2008-01-28

申请人： David K. Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

发明人： David K. Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11543

摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

摘要翻译： 本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。 在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度 以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。 在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路 包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

公开(公告)号：US20070218616A1

公开(公告)日：2007-09-20

申请号：US11377094

申请日：2006-03-16

申请人： Kunal Parekh

发明人： Kunal Parekh

IPC分类号： H01L21/8234

CPC分类号： H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is formed to comprise source/drain regions within the additional semiconductor material, and to comprise a channel between the source/drain regions. At least one of the source/drain regions is primarily directly over a segment of the dielectric material, and the channel is not primarily directly over any segment of the dielectric material. The invention also includes constructions comprising partial SOI corresponding to segments of dielectric material, and transistors having at least one source/drain region primarily directly over a segment of dielectric material, and a channel that is not primarily directly over any segment of the dielectric material.

摘要翻译： 本发明包括将部分SOI并入晶体管结构的方法。 在特定方面，电介质材料设置在半导体材料上，并被图案化成由间隙分开的至少两个段。 然后在电介质材料上并在间隙内生长附加的半导体材料。 随后，形成晶体管以在附加半导体材料内包括源极/漏极区域，并且包括在源极/漏极区域之间的沟道。 源极/漏极区域中的至少一个主要直接位于电介质材料的一段上，并且沟道不主要直接位于介电材料的任何部分上方。 本发明还包括包括对应于电介质材料段的部分SOI的构造，以及主要直接位于介电材料段上的至少一个源/漏区的晶体管，以及不主要直接位于电介质材料的任何段上的沟道。

公开(公告)号：US20060264019A1

公开(公告)日：2006-11-23

申请号：US11497598

申请日：2006-07-31

申请人： Kunal Parekh ,  John Zahurak

发明人： Kunal Parekh ,  John Zahurak

IPC分类号： H01L21/4763

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

摘要翻译： 本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。 在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。 在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与靠近晶体管的栅极的各向异性蚀刻的侧壁间隔开。

公开(公告)号：US20060263969A1

公开(公告)日：2006-11-23

申请号：US11132472

申请日：2005-05-19

申请人： David Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

发明人： David Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

IPC分类号： H01L21/8244

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11543

摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

公开(公告)号：US20060258087A1

公开(公告)日：2006-11-16

申请号：US11486524

申请日：2006-07-13

申请人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

发明人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/425 ,  H01L21/8238

CPC分类号： H01L29/66787 ,  H01L27/10808 ,  H01L27/10876

摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

公开(公告)号：US20060216894A1

公开(公告)日：2006-09-28

申请号：US11090529

申请日：2005-03-25

申请人： Kunal Parekh ,  Suraj Mathew ,  Jigish Trivedi ,  John Zahurak ,  Sanh Tang

发明人： Kunal Parekh ,  Suraj Mathew ,  Jigish Trivedi ,  John Zahurak ,  Sanh Tang

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

公开(公告)号：US20060211208A1

公开(公告)日：2006-09-21

申请号：US11418556

申请日：2006-05-05

申请人： Kunal Parekh ,  H. Manning

发明人： Kunal Parekh ,  H. Manning

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L21/28238 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/66553 ,  H01L29/66583

摘要： The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of dielectric material being within an opening. A gateline material is formed within the opening and over the thin and thicker segments of dielectric material. The construction comprising the gateline material over the thin and thicker segments of dielectric material can be supported by a semiconductor substrate having a primary surface which defines a horizontal direction. The thin and thicker segments of dielectric material can comprise upper surfaces substantially parallel to the primary surface of the substrate, and can join to one another at steps having primary surfaces substantially orthogonal to the primary surface of the substrate.