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公开(公告)号：US12002508B2
公开(公告)日：2024-06-04
申请号：US17450940
申请日：2021-10-14
发明人： Eran Sharon , Alon Marcu , Shay Benisty , Judah Gamliel Hahn , Idan Alrod , Alexander Bazarsky , Ariel Navon , Ran Zamir
IPC分类号： G11C11/56 , G06F9/30 , G11C8/16 , G11C11/065 , H03K19/1776 , H03K19/21
CPC分类号： G11C11/5628 , G06F9/3004 , G11C8/16 , G11C11/065 , H03K19/1776 , H03K19/21
摘要： The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.
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公开(公告)号：US11741025B2
公开(公告)日：2023-08-29
申请号：US17178401
申请日：2021-02-18
发明人： Shay Benisty , Ariel Navon , Judah Gamliel Hahn , Alon Marcu
CPC分类号： G06F13/1605 , G06F9/546
摘要： A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.
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公开(公告)号：US11158369B2
公开(公告)日：2021-10-26
申请号：US16232639
申请日：2018-12-26
发明人： Eran Sharon , Alon Marcu , Shay Benisty , Judah Gamliel Hahn , Idan Alrod , Alexander Bazarsky , Ariel Navon , Ran Zamir
IPC分类号： G11C11/56 , H03K19/21 , G06F9/30 , G11C8/16 , G11C11/065 , H03K19/1776
摘要： The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.
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公开(公告)号：US10910057B2
公开(公告)日：2021-02-02
申请号：US16390370
申请日：2019-04-22
发明人： Idan Alrod , Eran Sharon , Alon Marcu , Yan Li
摘要： A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.
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公开(公告)号：US20180359652A1
公开(公告)日：2018-12-13
申请号：US15621476
申请日：2017-06-13
发明人： Liran Sharoni , ldo Shilo , Miki Sapir , Alon Marcu
CPC分类号： H04W24/08 , G06F11/3034 , G06F11/3438 , G06F11/3466 , G06F11/3485 , G06F2201/86 , H04H60/64 , H04H60/85
摘要： A method and system for user experience event processing and analysis are provided. In one embodiment, a method is provided comprising: receiving a recorded video of a display of the host device and a reference video; comparing the recorded video with the reference video to identify differences, wherein the recorded video and the reference video are synchronized based on content rather than time; receiving data indicating activity of a storage device of the host device; correlating the differences with the data indicating activity of the storage device; and generating an analysis of the correlation. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
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公开(公告)号：US10154429B1
公开(公告)日：2018-12-11
申请号：US15621476
申请日：2017-06-13
发明人： Liran Sharoni , Ido Shilo , Miki Sapir , Alon Marcu
CPC分类号： H04W24/08 , G06F11/3034 , G06F11/3438 , G06F11/3466 , G06F11/3485 , G06F2201/86 , H04H60/64 , H04H60/85
摘要： A method and system for user experience event processing and analysis are provided. In one embodiment, a method is provided comprising: receiving a recorded video of a display of the host device and a reference video; comparing the recorded video with the reference video to identify differences, wherein the recorded video and the reference video are synchronized based on content rather than time; receiving data indicating activity of a storage device of the host device; correlating the differences with the data indicating activity of the storage device; and generating an analysis of the correlation. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
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公开(公告)号：US11681634B2
公开(公告)日：2023-06-20
申请号：US17142027
申请日：2021-01-05
发明人： Shay Benisty , Alon Marcu , Ariel Navon
IPC分类号： G06F3/06 , G06F12/1081 , G06F13/42
CPC分类号： G06F12/1081 , G06F3/0611 , G06F3/0635 , G06F3/0659 , G06F3/0679 , G06F13/4282 , G06F2213/0026
摘要： Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.
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公开(公告)号：US20230179777A1
公开(公告)日：2023-06-08
申请号：US18104176
申请日：2023-01-31
发明人： Alon Marcu , Ofir Pele , Ariel Navon , Shay Benisty , Karin Inbar , Judah Gamliel Hahn
IPC分类号： H04N19/176 , H04N19/159 , G11C16/04 , H04N19/52 , H04N19/58 , H04N19/103 , H04N19/513
CPC分类号： H04N19/176 , H04N19/159 , G11C16/0483 , H04N19/52 , H04N19/58 , H04N19/103 , H04N19/513
摘要： A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.
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公开(公告)号：US11188239B2
公开(公告)日：2021-11-30
申请号：US16368092
申请日：2019-03-28
发明人： Shay Benisty , Alon Marcu , Judah G. Hahn
IPC分类号： G06F3/06
摘要： A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) for storing data. A processor of the DSD receives a command from a host to access data in the NVM, and performs the command to access data in the NVM. The DSD further includes a host-trusted module functionally isolated from at least a portion of the DSD. The host-trusted module is configured to receive an instruction from the host, and perform an operation based on the instruction. According to one aspect, the operation includes a predetermined atomic operation to modify data stored in the NVM.
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公开(公告)号：US20210027838A1
公开(公告)日：2021-01-28
申请号：US17036889
申请日：2020-09-29
发明人： Idan Alrod , Eran Sharon , Alon Marcu , Yan Li
摘要： A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.
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