利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

29 条记录 (耗时 0.031 秒)

    Apparatus and method of data transfer between systems using different clocks
    4.
    发明授权
    Apparatus and method of data transfer between systems using different clocks 失效
    使用不同时钟的系统之间的数据传输的装置和方法

    公开(公告)号：US5347559A

    公开(公告)日：1994-09-13

    申请号：US998714

    申请日：1992-12-30

    申请人： Thomas B. Hawkins ,  William Bruckert ,  Thomas D. Bissett

    发明人： Thomas B. Hawkins ,  William Bruckert ,  Thomas D. Bissett

    IPC分类号： G06F1/12 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F13/28 ,  G06F13/42 ,  H03D13/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03K21/08

    CPC分类号： G06F1/12 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1683 ,  G06F13/28 ,  G06F13/4243 ,  H03L7/085 ,  H03L7/087 ,  G06F11/006 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1654 ,  G06F11/20 ,  G06F11/2205 ,  H03D13/003 ,  H03L7/089

    摘要： According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

    摘要翻译： 根据本发明的一个方面，一种装置包括耦合到第一系统总线以向高速缓存和存储器提供数据的第一处理器，以及耦合到第一系统总线的第二处理器和用于接收读取数据的第二缩写系统总线 从第一个系统总线。 根据本发明的另一方面，一种装置包括用于校正存储器中的错误的装置。 根据本发明的另一方面，一种装置包括多个计算系统，每个计算系统包括安装在不经常更换的硬件单元上并且能够与多个计算系统进行通信的存储器装置。 根据本发明的另一方面，一种装置包括计数器，用于检测所述计数器的选定状态的装置，以及响应于来自所述计数器的输出信号的装置，用于选择性地允许或禁止馈送到循环状态装置的数据的传送 。 根据本发明的另一方面，一种装置包括用于提供第一时钟信号的第一装置，用于提供第二时钟信号的第二装置，用于响应于第一和第二时钟信号的边缘之间的偏移而提供误差信号的装置 时钟信号。

    Method and apparatus for reducing checking costs in fault tolerant processors
    7.
    发明授权
    Method and apparatus for reducing checking costs in fault tolerant processors 失效
    降低容错处理器检查成本的方法和装置

    公开(公告)号：US5339408A

    公开(公告)日：1994-08-16

    申请号：US998715

    申请日：1992-12-30

    申请人： William Bruckert ,  Thomas D. Bissett ,  Glenn Dearth ,  Paul Paternoster

    发明人： William Bruckert ,  Thomas D. Bissett ,  Glenn Dearth ,  Paul Paternoster

    IPC分类号： G06F1/12 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F13/28 ,  G06F13/42 ,  H03D13/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089

    CPC分类号： G06F1/12 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1683 ,  G06F13/28 ,  G06F13/4243 ,  H03L7/085 ,  H03L7/087 ,  G06F11/006 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1654 ,  G06F11/20 ,  G06F11/2205 ,  H03D13/003 ,  H03L7/089

    摘要： According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

    摘要翻译： 根据本发明的一个方面，一种装置包括耦合到第一系统总线以向高速缓存和存储器提供数据的第一处理器，以及耦合到第一系统总线的第二处理器和用于接收读取数据的第二缩写系统总线 从第一个系统总线。 根据本发明的另一方面，一种装置包括用于校正存储器中的错误的装置。 根据本发明的另一方面，一种装置包括多个计算系统，每个计算系统包括安装在不经常更换的硬件单元上并且能够与多个计算系统进行通信的存储器装置。 根据本发明的另一方面，一种装置包括计数器，用于检测所述计数器的选定状态的装置，以及响应于来自所述计数器的输出信号的装置，用于选择性地允许或禁止馈送到循环状态装置的数据的传送 。 根据本发明的另一方面，一种装置包括用于提供第一时钟信号的第一装置，用于提供第二时钟信号的第二装置，用于响应于第一和第二时钟信号的边缘之间的偏移而提供误差信号的装置 时钟信号。

    Fault resilient/fault tolerant computing
    10.
    发明授权
    Fault resilient/fault tolerant computing 失效
    故障恢复/容错计算

    公开(公告)号：US5600784A

    公开(公告)日：1997-02-04

    申请号：US405193

    申请日：1995-03-16

    申请人： Thomas D. Bissett ,  Richard D. Fiorentino ,  Robert M. Glorioso ,  Diane T. McCauley ,  James D. McCollum ,  Glenn A. Tremblay

    发明人： Thomas D. Bissett ,  Richard D. Fiorentino ,  Robert M. Glorioso ,  Diane T. McCauley ,  James D. McCollum ,  Glenn A. Tremblay

    IPC分类号： G06F11/18 ,  G06F1/04 ,  G06F1/14 ,  G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/10 ,  G06F13/14 ,  G06F15/16 ,  G06F15/76 ,  G01R31/28

    CPC分类号： G06F11/1658 ,  G06F1/14 ,  G06F11/1645 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/2005 ,  G06F11/2017 ,  G06F11/1641 ,  G06F11/185

    摘要： In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing elements.Computer systems include one or more controllers and at least two computing elements. System is provided for intercepting I/O operations by the computing elements and transmitting them to the one or more controllers.

    摘要翻译： 在第一方面中，一种同步至少两个计算元件的方法，每个计算元件具有与其它计算元件的时钟异步工作的时钟，包括从由所述另一个计算元件产生的一组信号中选择一个或多个指定为元时间信号的信号 计算元件，监视所述计算元件以通过所述计算元件之一检测所选择的信号的产生，等待所述其他计算元件产生所选择的信号，向所述计算元件中的每一个发送等价的时间更新，以及更新所述时钟 的计算元素基于时间更新。 在第二方面，通过将第一处理器指定为计算元件，指定作为控制器的第二处理器，连接计算元件和控制器以产生模块对，并连接至少两个模块化 成对产生故障恢复或容错计算机。 计算机的每个计算元件执行与其它计算元件相同数量的循环的所有指令。 计算机系统包括一个或多个控制器和至少两个计算元件。 提供系统用于通过计算元件截取I / O操作并将其发送到一个或多个控制器。