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公开(公告)号：US20150006917A1
公开(公告)日：2015-01-01
申请号：US13930044
申请日：2013-06-28
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3246 , G06F1/3275 , G06F9/30083 , G06F9/30101 , G06F9/30189
摘要： In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括多个核。 每个核心包括用于检测一个或多个电力管理事件的核心电力单元，并且响应于一个或多个电力管理事件，在核心中发起受保护的电力管理模式。 在受保护的电源管理模式下，可能会禁用到核心的软件中断。 核心是在受保护的电源管理模式下执行电源管理代码。 描述和要求保护其他实施例。
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公开(公告)号：US20140281398A1
公开(公告)日：2014-09-18
申请号：US13844873
申请日：2013-03-16
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F9/3017 , G06F9/30189 , G06F9/382
摘要： A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.
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公开(公告)号：US20140283032A1
公开(公告)日：2014-09-18
申请号：US13839048
申请日：2013-03-15
IPC分类号： G06F21/57
CPC分类号： G06F21/57
摘要： Embodiments of an invention for inter-processor attestation hardware are disclosed. In one embodiment, an apparatus includes first attestation hardware associated with a first portion of a system. The first attestation hardware is to attest to a second portion of the system that the first portion of the system is secure.
摘要翻译： 公开了用于处理器间认证硬件的发明的实施例。 在一个实施例中，装置包括与系统的第一部分相关联的第一认证硬件。 第一个认证硬件是证明系统的第一部分是系统的第二部分是安全的。
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4.发明申请PROCESSORS, METHODS, AND SYSTEMS TO RELAX SYNCHRONIZATION OF ACCESSES TO SHARED MEMORY 有权处理器，方法和系统，以放大对共享存储器的访问同步公开(公告)号：US20140281196A1
公开(公告)日：2014-09-18
申请号：US13844729
申请日：2013-03-15
IPC分类号： G06F12/14
CPC分类号： G06F9/30087 , G06F12/0804 , G06F12/0815 , G06F12/0862 , G06F12/14 , G06F2212/1052 , G06F2212/6028 , G11C7/1072 , Y02D10/13
摘要： A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.
摘要翻译： 一个方面的处理器包括多个逻辑处理器。 多个的第一逻辑处理器是执行包括存储器访问同步指令的软件，所述存储器访问同步指令旨在同步对存储器的访问。 处理器还包括存储器访问同步放宽逻辑，当处理器处于松弛的存储器访问同步模式时，该存储器访问同步放松逻辑防止存储器访问同步指令同步对存储器的访问。
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公开(公告)号：US11080045B2
公开(公告)日：2021-08-03
申请号：US13993483
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.
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公开(公告)号：US20210103662A1
公开(公告)日：2021-04-08
申请号：US17127122
申请日：2020-12-18
申请人： Chinmay Ashok , Vasudevan Srinivasan , Atanas K. Iwanow , Martin G. Dixon , Scott J. Cape , Scott Bobholz , David T. Mayo , Vinila Rose , Lorie Wigle , Jason Kennedy
发明人： Chinmay Ashok , Vasudevan Srinivasan , Atanas K. Iwanow , Martin G. Dixon , Scott J. Cape , Scott Bobholz , David T. Mayo , Vinila Rose , Lorie Wigle , Jason Kennedy
摘要： Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.
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公开(公告)号：US09960917B2
公开(公告)日：2018-05-01
申请号：US13995453
申请日：2011-12-22
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
CPC分类号： H04L9/0631 , G06F9/30007 , G06F9/3001 , G06F9/30036 , H04L9/0643
摘要： A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.
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公开(公告)号：US09772845B2
公开(公告)日：2017-09-26
申请号：US13976184
申请日：2011-12-13
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
CPC分类号： G06F9/30145 , H04L9/0643 , H04L2209/122
摘要： A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.
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9.发明授权公开(公告)号：US09747105B2
公开(公告)日：2017-08-29
申请号：US12653704
申请日：2009-12-17
申请人： Vinodh Gopal , James D. Guilford , Erdine Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
发明人： Vinodh Gopal , James D. Guilford , Erdine Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3816 , G06F9/3893
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
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公开(公告)号：US09652234B2
公开(公告)日：2017-05-16
申请号：US13996352
申请日：2011-09-30
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.
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