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26 条记录 (耗时 0.022 秒)

    Hybrid voltage/current-mode transmission line driver
    1.
    发明申请
    Hybrid voltage/current-mode transmission line driver 有权
    混合电压/电流模式传输线驱动

    公开(公告)号：US20070002954A1

    公开(公告)日：2007-01-04

    申请号：US11173109

    申请日：2005-07-01

    申请人： William Cornelius ,  Matthew Herndon ,  Ronald Larson

    发明人： William Cornelius ,  Matthew Herndon ,  Ronald Larson

    IPC分类号： H04B3/00

    CPC分类号： H04B3/04

    摘要： A system that transmits signals through a communication channel. During operation, the system receives a sequence of bits for transmission through the communication channel. While transmitting a given bit, the system determines if the given bit has the same state as the previously transmitted bit. If so, the system uses a voltage-mode driver to drive a signal through the communication channel. Otherwise, the system uses a current source coupled to the voltage-mode driver to boost the drive-level of the voltage-mode driver. Note that the current source supplies a current to the communication channel without changing the impedance of the voltage-mode driver. In this way, the present invention compensates for frequency dependant losses in the communication channel without sacrificing impedance matching and without substantially increasing power consumption.

    摘要翻译： 通过通信信道发送信号的系统。 在操作期间，系统接收通过通信信道传输的比特序列。 在发送给定位时，系统确定给定位是否与先前发送的位具有相同的状态。 如果是这样，系统使用电压模式驱动器通过通信通道驱动信号。 否则，系统使用耦合到电压模式驱动器的电流源来提高电压模式驱动器的驱动电平。 注意，电流源向通信通道提供电流，而不改变电压模式驱动器的阻抗。 以这种方式，本发明补偿通信信道中的频率相关损耗，而不牺牲阻抗匹配并且基本上不增加功耗。

    Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains
    3.
    发明申请
    Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains 有权
    同步时钟子域之间校准的可变相位偏移定时的方法和装置

    公开(公告)号：US20050021920A1

    公开(公告)日：2005-01-27

    申请号：US10919668

    申请日：2004-08-16

    申请人： William Cornelius ,  Minoru Taoyama ,  Paul Thompson

    发明人： William Cornelius ,  Minoru Taoyama ,  Paul Thompson

    IPC分类号： G06F1/10 ,  G06F12/00 ,  G06F13/16

    CPC分类号： G06F13/1689 ,  G06F1/10

    摘要： A method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains is described. In one embodiment, the invention is an apparatus. The apparatus includes a first subsystem and a second subsystem coupled to the first subsystem. The apparatus also includes a clock signal generator coupled to the first subsystem and coupled to the second subsystem. The clock signal generator is to supply a first clock to the first subsystem and to supply a second clock to the first subsystem and to supply a third clock to the second subsystem. Each of the first clock, the second clock and the third clock are derived from a common clock, the first clock having a first predetermined phase offset relative to the third clock, and the second clock having a second predetermined phase offset relative to the third clock. The first predetermined phase offset and the second predetermined phase offset are adjustable based on performance characteristics of the first subsystem and performance characteristics of the second subsystem.

    摘要翻译： 描述了用于同步时钟子域之间校准的可变相位偏移定时的方法和装置。 在一个实施例中，本发明是一种装置。 该装置包括耦合到第一子系统的第一子系统和第二子系统。 该装置还包括耦合到第一子系统并耦合到第二子系统的时钟信号发生器。 时钟信号发生器将第一时钟提供给第一子系统，并向第一子系统提供第二时钟并向第二子系统提供第三时钟。 第一时钟，第二时钟和第三时钟中的每一个从公共时钟导出，第一时钟具有相对于第三时钟的第一预定相位偏移，并且第二时钟具有相对于第三时钟的第二预定相位偏移 。 第一预定相位偏移和第二预定相位偏移可基于第一子系统的性能特征和第二子系统的性能特性来调节。

    Single-ended balance-coded interface with embedded-timing
    6.
    发明授权
    Single-ended balance-coded interface with embedded-timing 失效
    具有嵌入式时序的单端平衡编码接口

    公开(公告)号：US06734811B1

    公开(公告)日：2004-05-11

    申请号：US10443547

    申请日：2003-05-21

    申请人： William Cornelius

    发明人： William Cornelius

    IPC分类号： H03M500

    CPC分类号： H03M5/06 ,  H03M7/46

    摘要： An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

    摘要翻译： 接口包括用于接收输入符号流的编码器，并且作为响应，经由多个信号线输出基本相等权重的对应的输出符号流，这可以改善噪声/速度性能。 编码器输出输出符号流，使得不输出符号被连续重复。 重复符号用于表示当前符号与前一个符号相同。 该编码允许接收输出符号流的接口可以从流中提取时钟信号。

    MICRODVI CONNECTOR
    8.
    发明申请
    MICRODVI CONNECTOR 有权
    MICRODVI连接器

    公开(公告)号：US20090186527A1

    公开(公告)日：2009-07-23

    申请号：US12242784

    申请日：2008-09-30

    申请人： Dave Hardell ,  Glenn E. Wheelock ,  Chris Ligtenberg ,  Steve Sfarzo ,  William Cornelius ,  Bartley K. Andre

    发明人： Dave Hardell ,  Glenn E. Wheelock ,  Chris Ligtenberg ,  Steve Sfarzo ,  William Cornelius ,  Bartley K. Andre

    IPC分类号： H01R24/00

    CPC分类号： H01R13/6471 ,  G09G5/006 ,  H01R12/724 ,  H01R13/64 ,  H01R13/6473

    摘要： A small form-factor, high performance connector is disclosed. This connector is intended for use with high bandwidth digital video, implementing differential digital signaling, as well as for high bandwidth analog video. The described connector system performs the function of the Digital Visual Interface (DVI) connector, but in a significantly smaller package. Signal integrity is maintained in the smaller form factor by the expedient assignment of signals to pins so that the pin above or below any signal is not used on that interface, thus reducing the chances for signal crosstalk. The pin shape and spacing are created to match pin lengths and minimize inductance while maintaining the proper impedance up to 2.5 GHz. This connector system also implements a tactile feedback mechanism to aid with cable plug insertion, and incorporates a keying mechanism to prevent reverse-plugging.

    摘要翻译： 公开了一种小尺寸的高性能连接器。 该连接器适用于高带宽数字视频，实现差分数字信号以及高带宽模拟视频。 所描述的连接器系统执行数字视觉接口（DVI）连接器的功能，但是在显着更小的封装中。 通过将信号方便地分配给引脚，使信号完整性保持在更小的形状因数，使得在该接口上不使用任何信号上方或下方的引脚，从而降低信号串扰的机会。 创建引脚形状和间距以匹配引脚长度并最小化电感，同时保持高达2.5 GHz的适当阻抗。 该连接器系统还实现了触觉反馈机制，以帮助电缆插头插入，并结合了键控机构以防止反向插入。

    Method and apparatus for selectively switching IC ports to card slots
    9.
    发明申请
    Method and apparatus for selectively switching IC ports to card slots 失效
    用于选择性地将IC端口切换到卡槽的方法和装置

    公开(公告)号：US20070239904A1

    公开(公告)日：2007-10-11

    申请号：US11304439

    申请日：2005-12-14

    申请人： William Cornelius ,  Paul Baker ,  Joseph Bratt

    发明人： William Cornelius ,  Paul Baker ,  Joseph Bratt

    IPC分类号： G06F3/00 ,  H05K7/10

    CPC分类号： G06F1/22

    摘要： A system that selectively couples one or more IC chips to card slots. The system contains a Z-bar switch which includes: a select input; a first IC port coupled to a first IC pin; a second IC port coupled to a second IC pin; a first card slot port coupled to a first card slot pin; and a second card slot port coupled to a second card slot pin. If the select input receives a first control pattern, the Z-bar switch is configured to: couple the first IC port to the first card slot port; and to couple the second IC port to the second card slot port. If the select input receives a second control pattern, the Z-bar switch is configured to: couple the first IC port to the second card slot port; leave the second IC port floating; and to leave the first card slot port floating.

    摘要翻译： 将一个或多个IC芯片选择性地耦合到卡插槽的系统。 该系统包含一个Z-bar开关，它包括：一个选择输入; 耦合到第一IC引脚的第一IC端口; 耦合到第二IC引脚的第二IC端口; 耦合到第一卡槽销的第一卡槽口; 以及耦合到第二卡槽销的第二卡槽口。 如果选择输入接收到第一控制模式，则Z-bar开关被配置为：将第一IC端口耦合到第一卡插槽端口; 并将第二IC端口耦合到第二卡槽口。 如果选择输入接收到第二控制模式，则Z-bar开关被配置为：将第一IC端口耦合到第二卡插槽端口; 离开第二个IC端口; 并离开第一个卡槽口浮动。

    Reducing the number of power and ground pins required to drive address signals to memory modules
    10.
    发明申请
    Reducing the number of power and ground pins required to drive address signals to memory modules 有权
    减少将地址信号驱动到内存模块所需的电源和接地引脚数

    公开(公告)号：US20060039205A1

    公开(公告)日：2006-02-23

    申请号：US10925174

    申请日：2004-08-23

    申请人： William Cornelius

    发明人： William Cornelius

    IPC分类号： G11C7/10 ,  G11C8/00

    CPC分类号： G11C5/066 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/1045 ,  Y02D10/14

    摘要： One embodiment of the present invention provides a system that reduces the number of power and ground pins required to drive address signals to system memory. During operation, the system receives address signals associated with a memory operation from a memory controller, wherein the address signals are received at a buffer chip, which is external the memory controller. The system also receives chip select signals associated with the memory operation at the buffer chip. Next, the system uses the chip select signals to identify an active subset of memory modules in the system memory, which are active during the memory operation. The system then uses address drivers on the buffer chip to drive the address signals only to the active subset of memory modules, and not to other memory modules in the system memory. In this way, the buffer chip requires fewer power and ground pins for the address drivers because the address signals are only driven to the active subset of memory modules, instead of being driven to all memory modules in the system memory.

    摘要翻译： 本发明的一个实施例提供一种减少将地址信号驱动到系统存储器所需的电源和接地引脚数的系统。 在操作期间，系统从存储器控制器接收与存储器操作相关联的地址信号，其中地址信号在存储器控制器外部的缓冲器芯片处被接收。 该系统还接收与缓冲器芯片上的存储器操作相关联的片选信号。 接下来，系统使用芯片选择信号来识别系统存储器中的存储器模块的活动子集，其在存储器操作期间是活动的。 系统然后使用缓冲芯片上的地址驱动程序将地址信号驱动到内存模块的有效子集，而不是系统内存中的其他内存模块。 这样，由于地址信号仅被驱动到存储器模块的有源子集而不是被驱动到系统存储器中的所有存储器模块，所以缓冲器芯片对于地址驱动器需要较少的电源和接地引脚。