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    Method for fabrication of improved storage target and target produced thereby
    1.
    发明授权
    Method for fabrication of improved storage target and target produced thereby 失效
    制造改进的存储目标和由此产生的目标的方法

    公开(公告)号：US4212082A

    公开(公告)日：1980-07-08

    申请号：US898620

    申请日：1978-04-21

    申请人： William D. Barber ,  George E. Possin

    发明人： William D. Barber ,  George E. Possin

    IPC分类号： G11C11/23 ,  G11C13/02 ,  C25D11/32

    CPC分类号： G11C11/23

    摘要： An improved target for storage of electric charge, in an electron beam addressable memory, utilizes an anodic oxide grown upon a semiconductor layer, forming part of a semiconductor diode structure. The anodic oxide is overlayed with a planar film of conductive material and the target structure is scanned with an electron beam for writing of electric charge storage therein and reading of the electron charge patterns therefrom over relatively greater numbers of erase/write operations relative to a target having a thermally-grown oxide layer.

    摘要翻译： 在电子束可寻址存储器中，用于存储电荷的改进目标利用在半导体层上生长的阳极氧化物，形成半导体二极管结构的一部分。 阳极氧化物覆盖有导电材料的平面膜，并且目标结构用用于写入电荷的电子束扫描，并且通过相对于目标的相对较多数量的擦除/写入操作读取电子电荷模式 具有热生长的氧化物层。

    Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface
    2.
    发明授权
    Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface 失效
    利用栅极电介质/半导体层界面的氢等离子体处理制造薄膜晶体管的方法

    公开(公告)号：US5273920A

    公开(公告)日：1993-12-28

    申请号：US939746

    申请日：1992-09-02

    申请人： Robert F. Kwasnick ,  George E. Possin

    发明人： Robert F. Kwasnick ,  George E. Possin

    IPC分类号： H01L21/30 ,  H01L29/786 ,  H01L21/265

    CPC分类号： H01L29/4908 ,  H01L21/3003 ,  H01L29/66765 ,  H01L29/78669 ,  Y10S438/91

    摘要： A method of fabricating a thin film transistor (TFT) includes the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer of silicon nitride over the gate conductor; treating the exposed silicon nitride on the surface of the gate dielectric layer with a hydrogen plasma at a power level of at least 44 mW/cm.sup.2 for at least 5 minutes; depositing a layer of amorphous silicon semiconductor material over the gate dielectric layer; depositing a layer of n+ doped silicon over the treated amorphous silicon surface; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The deposition of the TFT material layers and the hydrogen plasma treatment is preferably by plasma enhanced chemical vapor deposition.

    摘要翻译： 制造薄膜晶体管（TFT）的方法包括在基板上形成栅极导体的步骤; 在栅极导体上沉积氮化硅栅极电介质层; 用至少44mW / cm 2的功率水平的氢等离子体处理所述栅极电介质层的表面上暴露的氮化硅至少5分钟; 在所述栅极电介质层上沉积非晶硅半导体材料层; 在所处理的非晶硅表面上沉积n +掺杂硅层; 在n +掺杂层上沉积一层源极/漏极金属化层; 以及图案化源极/漏极金属化层和下层n +掺杂层的部分以形成源极和漏极。 TFT材料层的沉积和氢等离子体处理优选通过等离子体增强化学气相沉积。

    Fabrication method for a self-aligned thin film transistor having reduced end leakage and device formed thereby
    3.
    发明授权
    Fabrication method for a self-aligned thin film transistor having reduced end leakage and device formed thereby 失效
    具有减小的端部泄漏的自对准薄膜晶体管的制造方法以及由此形成的器件

    公开(公告)号：US5241192A

    公开(公告)日：1993-08-31

    申请号：US862125

    申请日：1992-04-02

    申请人： George E. Possin ,  Ching-Yeu Wei

    发明人： George E. Possin ,  Ching-Yeu Wei

    IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786

    CPC分类号： H01L29/78696 ,  H01L27/1214 ,  H01L29/66765 ,  Y10S438/978

    摘要： The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.

    摘要翻译： 根据本发明形成的TFT结构包括TFT体，其具有分隔等于或小于源极/漏极地址线的宽度的距离的通道插塞端侧壁，并且使得没有残留的掺杂半导体材料粘附到侧壁。 类似地，本征半导体材料层被成形为使得没有残留掺杂的半导体材料粘附到通道插塞下面的本征半导体材料层的侧壁终止。

    Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration
    4.
    发明授权
    Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration 失效
    通过顶帽栅极电极配置对自对准TFTS中的源极/漏极 - 栅极重叠进行正向控制

    公开(公告)号：US5156986A

    公开(公告)日：1992-10-20

    申请号：US667149

    申请日：1991-03-11

    申请人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

    发明人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49

    CPC分类号： H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/4908

    摘要： Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.

    摘要翻译： 通过包括具有不同蚀刻特性的两个不同导体的栅极导体层来提供薄膜晶体管中的栅极电极和源极和漏极之间的重叠长度的正向控制。 作为栅极导体图案定义过程的一部分，蚀刻两个栅极导体以暴露下面的材料，并且根据栅电极和源之间的期望重叠，蚀刻回去上栅极导体层以暴露第一栅极导体层，以及 漏电极。 此后，使用平面化和非选择性蚀刻方法，用相对于第二栅极导体层自对准的源极和漏极制造器件的其余部分。

    Hybrid energy discriminating charge integrating CT detector
    9.
    发明授权
    Hybrid energy discriminating charge integrating CT detector 有权
    混合能量鉴别电荷整合CT检测器

    公开(公告)号：US07512210B2

    公开(公告)日：2009-03-31

    申请号：US11692104

    申请日：2007-03-27

    申请人： George E. Possin ,  Kent C. Burr ,  Aaron J. Couture ,  Jonathan D. Short

    发明人： George E. Possin ,  Kent C. Burr ,  Aaron J. Couture ,  Jonathan D. Short

    IPC分类号： G01T1/24

    CPC分类号： G01T1/2985 ,  A61B6/032 ,  G01T1/2018

    摘要： An imaging system includes a gantry having a bore therethrough designed to receive a patient being translated through the bore an x-ray source disposed in the gantry and configured to emit x-rays toward the patient, and a detector module disposed in the gantry to receive x-rays attenuated by the patient. The detector module includes a scintillator configured to absorb the x-rays and to convert the x-rays into optical photons, a device configured to receive the optical photons and to convert the optical photons to electrical signals, and an adaptive data acquisition system (DAS) configured to switch an operating mode of the device from a charge integrating mode to a photon counting mode, and vice versa.

    摘要翻译： 成像系统包括具有穿过其中的孔的机架，其被设计成接收通过所述孔翻转的患者，设置在所述台架中的x射线源并且被配置为朝向患者发射x射线;以及检测器模块，设置在所述台架中以接收 由患者衰减的x射线。 检测器模块包括被配置为吸收x射线并将x射线转换成光学光子的闪烁器，被配置为接收光学光子并将光学光子转换成电信号的器件，以及自适应数据采集系统（DAS ）被配置为将器件的操作模式从电荷积分模式切换到光子计数模式，反之亦然。

    Solid state fluoroscopic radiation imager with thin film transistor addressable array
    10.
    发明授权
    Solid state fluoroscopic radiation imager with thin film transistor addressable array 失效
    具有薄膜晶体管可寻址阵列的固态荧光成像仪

    公开(公告)号：US5587591A

    公开(公告)日：1996-12-24

    申请号：US174921

    申请日：1993-12-29

    申请人： Jack D. Kingsley ,  George E. Possin

    发明人： Jack D. Kingsley ,  George E. Possin

    IPC分类号： G01T1/20 ,  G01T1/24 ,  G01T1/29 ,  H01L29/786 ,  H01L29/04

    CPC分类号： G01T1/2928 ,  G01T1/2018

    摘要： A low noise fluoroscopic radiation imager includes a large area photosensor array having a plurality of photosensors arranged in a pattern so as to have a predetermined pitch, and a low noise addressable thin film transistor (TFT) array electrically coupled to the photosensors. The TFT array includes a plurality of low charge retention TFTs, each of which have a switched silicon region that has an area in microns not greater than the value of the pitch of the imager array expressed in microns. The portion of the switched silicon region underlying the source and drain electrodes of the TFT is not greater than about 150% of the portion of the switched silicon region in the channel area of the TFT. The ratio of the TFT channel width to channel length (the distance between the source and drain electrodes across the channel) is less than 20:1, and commonly less than 10:1, with the channel length in the range of between about 1 .mu.m and 4 .mu.m. The photosensor array also includes crossover regions between address lines that have substantially no silicon therebetween so that no switched silicon region exists at the crossovers.

    摘要翻译： 低噪声荧光透射成像仪包括具有以预定间距排列成图案的多个光电传感器的大面积光电传感器阵列，以及与光电传感器电耦合的低噪声可寻址薄膜晶体管（TFT）阵列。 TFT阵列包括多个低电荷保持TFT，每个TFT具有开关硅区域，其面积微米不大于以微米表示的成像器阵列的间距值。 在TFT的源电极和漏电极下面的开关硅区域的部分不大于TFT沟道区域中开关硅区域的部分的约150％。 TFT沟道宽度与沟道长度的比率（源极和漏极之间的沟道间距离）小于20：1，通常小于10：1，沟道长度在约1微米之间 m和4亩。 光传感器阵列还包括地址线之间的交叉区域，它们之间基本上不具有硅，使得在交叉点处不存在交换的硅区域。