公开(公告)号：US4338663A

公开(公告)日：1982-07-06

申请号：US188291

申请日：1980-09-18

申请人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

发明人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/355 ,  G06F9/42 ,  G06F9/40

CPC分类号： G06F9/3555 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/355 ,  G06F9/4426

摘要： A digital data processing system with a central processor for responding to diverse instructions including instructions for calling subroutines. When the central processor executes a calling instruction, the central processor saves information corresponding to the operating environment for the calling routine and then utilizes corresponding information in the subroutine to establish the operating environment for the subroutine. A common return instruction at the completion of each subroutine causes the central processor to retrieve the saved operating information thereby to reestablish the operating environment for the calling routine.

摘要翻译： 一种具有中央处理器的数字数据处理系统，用于响应包括用于调用子程序的指令的各种指令。 当中央处理器执行调用指令时，中央处理器保存与调用例程的操作环境相对应的信息，然后利用子程序中的相应信息来建立子程序的操作环境。 在每个子程序完成时的公共返回指令使得中央处理器检索保存的操作信息，从而重新建立调用例程的操作环境。

公开(公告)号：US4241397A

公开(公告)日：1980-12-23

申请号：US954454

申请日：1978-10-25

申请人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

发明人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F9/36

CPC分类号： G06F9/355

摘要： A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

摘要翻译： 一种具有中央处理器的数字数据处理系统，用于响应具有可变长度的多种指令。 每条指令都包含一个操作代码。 某些指令还包括一个或多个操作数说明符。 每个操作数说明符可以包括一个或多个数据字节。 每条指令都传递给指令缓冲区。 中央处理器中的控制电路解码操作码，并依次对每个操作数说明符字节进行解码。 组合操作数说明符和从与操作数说明符有关的操作码导出的信息，以获得操作数要检索的地址或要传送操作数的地址。 中央处理器响应于用于添加位于第一和第二存储位置中的两个加法器并将和存储在第三位置中的指令，以及用于调用子程序以及从子程序返回到调用例程的指令。

公开(公告)号：US4241399A

公开(公告)日：1980-12-23

申请号：US954602

申请日：1978-10-25

申请人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

发明人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/42

CPC分类号： G06F9/30167 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/4426

摘要： A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

摘要翻译： 一种具有中央处理器的数字数据处理系统，用于响应具有可变长度的多种指令。 每条指令都包含一个操作代码。 某些指令还包括一个或多个操作数说明符。 每个操作数说明符可以包括一个或多个数据字节。 每条指令都传递给指令缓冲区。 中央处理器中的控制电路解码操作码，并依次对每个操作数说明符字节进行解码。 组合操作数说明符和从与操作数说明符有关的操作码导出的信息，以获得操作数要检索的地址或要传送操作数的地址。 中央处理器响应于用于添加位于第一和第二存储位置中的两个加法器并将和存储在第三位置中的指令，以及用于调用子程序以及从子程序返回到调用例程的指令。

公开(公告)号：US4236206A

公开(公告)日：1980-11-25

申请号：US954453

申请日：1978-10-25

申请人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

发明人： William D. Strecker ,  Thomas N. Hastings ,  Richard F. Lary ,  David P. Rodgers ,  Steven H. Rothman

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/40 ,  G06F9/34 ,  G06F9/36

CPC分类号： G06F9/35 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/4425

摘要： A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

摘要翻译： 一种具有中央处理器的数字数据处理系统，用于响应具有可变长度的多种指令。 每条指令都包含一个操作代码。 某些指令还包括一个或多个操作数说明符。 每个操作数说明符可以包括一个或多个数据字节。 每条指令都传递给指令缓冲区。 中央处理器中的控制电路解码操作码，并依次对每个操作数说明符字节进行解码。 组合操作数说明符和从与操作数说明符有关的操作码导出的信息，以获得操作数要检索的地址或要传送操作数的地址。 中央处理器响应于用于添加位于第一和第二存储位置中的两个加法器并将和存储在第三位置中的指令，以及用于调用子程序以及从子程序返回到调用例程的指令。

公开(公告)号：US06775790B2

公开(公告)日：2004-08-10

申请号：US09872980

申请日：2001-06-01

申请人： James M. Reuter ,  David W. Thiel ,  Richard F. Lary

发明人： James M. Reuter ,  David W. Thiel ,  Richard F. Lary

IPC分类号： G06F1210

CPC分类号： G06F3/0605 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0617 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1435 ,  G06F11/1451

摘要： The present invention provides a virtual storage system that generally stores uses larger segmentations, but divides large segments into smaller sub-segments during data movement operations. The present invention provides a method and system having this hierarchy of segment sizes, namely a large segment for the normal case, while breaking the large segment into single disk blocks during data movement. The mapping has large segments except for those segments undergoing data movement. For those segments, it would be desirable to have the smallest segment size possible, namely, a single disk block. In this way, the administration costs are generally low, but latencies caused by the movement of large data blocks are avoided.

摘要翻译： 本发明提供一种虚拟存储系统，其通常存储使用更大的分段，但是在数据移动操作期间将大段划分成更小的子段。 本发明提供了一种方法和系统，其具有这种分段大小的层级，即用于正常情况的大段，同时在数据移动期间将大段分割成单个磁盘块。 映射具有大的段，除了正在进行数据移动的段。 对于这些段，希望具有可能的最小段大小，即单个磁盘块。 这样，管理成本通常较低，但是避免了由大数据块移动引起的延迟。

公开(公告)号：US4434487A

公开(公告)日：1984-02-28

申请号：US308771

申请日：1981-10-05

申请人： Barry L. Rubinson ,  Mark A. Parenti ,  Richard F. Lary ,  Edward A. Gardner

发明人： Barry L. Rubinson ,  Mark A. Parenti ,  Richard F. Lary ,  Edward A. Gardner

IPC分类号： G06F3/06 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G06F11/10

CPC分类号： G11B20/1883 ,  G11B20/1252 ,  G11B20/1803 ,  G11B2220/20 ,  G11B2220/2508

摘要： In a disk mass storage facility for data processing systems, a disk format which improves handling of defective segments of medium and reduces access time. The format has three layers. A first, physical layer comprises the bytes, sectors and collections of sectors, as well as error detection and correction codes. A second, logical layer is used to address the physical layer and to collect together sectors to form a multiplicity of separately addressable spaces, with each space having a distinct functional utility. At a third, functional layer the use of data fields in each space is specified. This layer governs the handling of bad blocks if required, and the use of certain format information. Handling of bad blocks is controlled by a hierarchically layered process. A portion of each disc, distributed across the medium, is reserved as spare sectors to replace defective sectors. After a bad sector is replaced, future attempts to access the bad sector are redirected (i.e., revectored) to the replacement sector. For the simplest revectoring, the bad block is replaced by a replacement block in a known location. If that cannot be done, multiple copies of the replacement block's header are stored in the bad block's data field and the copies are compared to find the replacement address. If the comparison fails, or the header cannot be read, a back-up table is available to match the available replacement addresses with the original address which was replaced. A special code is used to identify blocks wherein the medium is good but the contents of the block are logically corrupted.

公开(公告)号：US06996691B2

公开(公告)日：2006-02-07

申请号：US10652328

申请日：2003-08-29

申请人： Stephen J. Sicola ,  Susan G. Elkington ,  Michael D. Walker ,  Richard F. Lary

发明人： Stephen J. Sicola ,  Susan G. Elkington ,  Michael D. Walker ,  Richard F. Lary

IPC分类号： G06F12/00

CPC分类号： G06F11/201 ,  G06F11/2007 ,  G06F11/2064 ,  G06F11/2071 ,  H04L1/16 ,  H04L1/22 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A disaster-tolerant data backup and remote copy system which is implemented as a controller-based replication of one or more LUNs (logical units) between two remotely separated pairs of array controllers connected by redundant links. The system provides a method for allowing a large number of commands to be ‘outstanding’ in transit between local and remote sites while ensuring the proper ordering of commands on remote media during asynchronous or synchronous data replication. In addition, the system provides a mechanism for automatic ‘tuning’ of links based on the distance between the array controllers.

公开(公告)号：US06601187B1

公开(公告)日：2003-07-29

申请号：US09539745

申请日：2000-03-31

申请人： Stephen J. Sicola ,  Susan G. Elkington ,  Michael D. Walker ,  Paul Guttormson ,  Richard F. Lary

发明人： Stephen J. Sicola ,  Susan G. Elkington ,  Michael D. Walker ,  Paul Guttormson ,  Richard F. Lary

IPC分类号： G06F1100

CPC分类号： G06F11/2071 ,  G06F11/2064 ,  H04L49/357 ,  H04L49/552 ,  H04L49/557

摘要： A data replication system having a redundant configuration including dual Fibre Channel fabric links interconnecting each of the components of two data storage sites, wherein each site comprises a host computer and associated data storage array, with redundant array controllers and adapters. Each array controller in the system is capable of performing all of the data replication functions, and each host ‘sees’ remote data as if it were local. Each array controller has a dedicated link via a fabric to a partner on the remote side of the long-distance link between fabric elements. Each dedicated link does not appear to any host as an available link to them for data access; however, it is visible to the partner array controllers involved in data replication operations. These links are managed by each partner array controller as if being ‘clustered’ with a reliable data link between them.

摘要翻译： 具有冗余配置的数据复制系统，其包括互连两个数据存储站点的每个组件的双光纤通道结构链路，其中每个站点包括具有冗余阵列控制器和适配器的主计算机和相关联的数据存储阵列。 系统中的每个阵列控制器都能够执行所有的数据复制功能，并且每个主机“看到”远程数据就好像它是本地的。每个阵列控制器都有一个通过一个结构的专用链路， 架构元素之间的长距离链接每个专用链路不会显示为任何主机作为可用的链接，用于数据访问;但是，对于涉及数据复制操作的合作伙伴阵列控制器可见，这些链接由每个合作伙伴管理 数组控制器就像在它们之间具有可靠的数据链接“聚集”一样。

公开(公告)号：US5659739A

公开(公告)日：1997-08-19

申请号：US538113

申请日：1995-10-02

申请人： Clark E. Lubbers ,  Susan G. Elkington ,  Richard F. Lary

发明人： Clark E. Lubbers ,  Susan G. Elkington ,  Richard F. Lary

IPC分类号： G06F17/30

CPC分类号： G06F17/30958 ,  Y10S707/99943

摘要： A system and technique for optimizing the efficiency of maintenance operations performed on skip lists of data elements or nodes stored in memory is provided. Each node of a skip list includes a back pointer for pointing to an immediate predecessor node and a node level field for recording the node level associated with the node. The system further includes a system agent for operating on the data structure, the system agent capable of locating the address of the immediate predecessor node pointing to a selected node by using the back pointer in the selected node.

摘要翻译： 提供了一种用于优化在存储在存储器中的数据元素或节点的跳过列表上执行的维护操作的效率的系统和技术。 跳过列表的每个节点包括用于指向直接前导节点的后向指针和用于记录与节点相关联的节点级别的节点级别字段。 所述系统还包括用于对所述数据结构进行操作的系统代理，所述系统代理能够通过使用所选节点中的所述后向指针来定位指向所选择的节点的所述直接前导节点的地址。

公开(公告)号：US5197143A

公开(公告)日：1993-03-23

申请号：US591088

申请日：1990-10-01

申请人： Richard F. Lary ,  William R. Bidermann ,  Timothy E. Nerger ,  John C. Lyle

发明人： Richard F. Lary ,  William R. Bidermann ,  Timothy E. Nerger ,  John C. Lyle

IPC分类号： G06F3/06 ,  G06F12/00

CPC分类号： G06F3/0601 ,  G06F2003/0692

摘要： A pipelined multi-staged logic control device for controlling the movement of information between a number of storage devices and a host computer. The pipelined multi-staged logic control device resides in a controller having a first and a second data bus wherein each of the data buses can access up to four drive ports. Information can flow through either of the data buses to any one of the eight total drive ports. A pair of indentical integrated circuit chips are each coupled individually to a single state machine. Each of the integrated circuit chips act in concert with their associated state machine to examine the state of the drive ports and to decide if a requested drive port can be accessed. The present invention is extremely fast due to the use of state machines. While a pickup head is locating information on a storage device, other requests for information are checked during this time to determine whether additional requests can be satisfied during the pickup head's locate time.

摘要翻译： 一种用于控制多个存储设备和主计算机之间的信息移动的流水线多级逻辑控制设备。 流水线化的多级逻辑控制装置驻留在具有第一和第二数据总线的控制器中，其中每个数据总线可以访问多达四个驱动端口。 信息可以通过任一数据总线进入八个总驱动端口中的任何一个。 一对独立的集成电路芯片分别连接到单个状态机。 每个集成电路芯片与其相关联的状态机协调工作，以检查驱动端口的状态并确定是否可以访问请求的驱动器端口。 由于使用状态机，本发明非常快。 当拾取头在存储设备上定位信息时，在此期间检查其他信息请求，以确定在拾取头的定位时间期间是否可以满足附加请求。