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265 条记录 (耗时 0.055 秒)

    Gate array with multiple dielectric properties and method for forming same
    1.
    发明授权
    Gate array with multiple dielectric properties and method for forming same 失效
    具有多种介电特性的门阵列及其形成方法

    公开(公告)号：US06563183B1

    公开(公告)日：2003-05-13

    申请号：US10085949

    申请日：2002-02-28

    申请人： William G. En ,  Arvind Halliyal ,  Minh-Ren Lin ,  Minh Van Ngo ,  Cyrus E. Tabery ,  Chih-Yuh Yang

    发明人： William G. En ,  Arvind Halliyal ,  Minh-Ren Lin ,  Minh Van Ngo ,  Cyrus E. Tabery ,  Chih-Yuh Yang

    IPC分类号： H01L2976

    CPC分类号： H01L21/823425 ,  H01L21/823462

    摘要： The invention provides an integrated circuit fabricated on a semiconductor substrate. The integrated circuit comprises a first field effect transistor and a second field effect transistor. The first field effect transistor comprises a first polysilicon gate positioned above a first channel region of the substrate and isolated from the first channel region by a first dielectric layer extending the entire length of the first polysilicon gate. The first dielectric layer comprises a first dielectric material with a first dielectric constant. The second field effect transistor comprises a second polysilicon gate positioned above a second channel region on the substrate and isolated from the second channel region by a second dielectric layer extending the entire length of the second polysilicon gate. The second dielectric layer comprises a second dielectric material with a second dielectric constant. The first dielectric constant and the second dielectric constant may be different and both may be greater than the dielectric constant of silicon dioxide.

    摘要翻译： 本发明提供一种在半导体衬底上制造的集成电路。 集成电路包括第一场效应晶体管和第二场效应晶体管。 第一场效应晶体管包括位于衬底的第一沟道区上方的第一多晶硅栅极，并通过延伸第一多晶硅栅极的整个长度的第一电介质层与第一沟道区隔离。 第一电介质层包括具有第一介电常数的第一电介质材料。 第二场效应晶体管包括位于衬底上的第二沟道区上方的第二多晶硅栅极，并且通过延伸第二多晶硅栅极的整个长度的第二电介质层与第二沟道区隔离。 第二电介质层包括具有第二介电常数的第二电介质材料。 第一介电常数和第二介电常数可以是不同的，并且它们都可以大于二氧化硅的介电常数。

    Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer
    2.
    发明授权
    Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer 有权
    确定用于图案化薄膜半导体层的抗反射涂层厚度的方法

    公开(公告)号：US06599766B1

    公开(公告)日：2003-07-29

    申请号：US10093596

    申请日：2002-03-08

    申请人： Cyrus E. Tabery ,  Chih-Yuh Yang ,  Minh Van Ngo

    发明人： Cyrus E. Tabery ,  Chih-Yuh Yang ,  Minh Van Ngo

    IPC分类号： H01L2100

    CPC分类号： G03F7/091 ,  G02B1/115

    摘要： The invention provides a method of selecting an anti reflective layer thickness for patterning a thin film silicon gate layer over a high K dielectric layer. The method comprises selecting a trial anti reflective layer thickness. A first coherent illumination intensity reflected from an interface between the photoresist layer and the anti reflective layer is calculated at the lithography wavelength. A second coherent illumination intensity reflected from an interface between the anti reflective layer and the polysilicon layer is calculated at the lithography wavelength. And, a third coherent illumination intensity reflected from an interface between the polysilicon layer and the high K dielectric layer is calculated at the lithography wavelength. A total coherent illumination intensity that comprises the sum of the first coherent illumination intensity, the second coherent illumination intensity, and the third coherent illumination intensity is calculated and compared to a predetermined threshold. If below the threshold, the trail anti reflective layer thickness is selected as the anti reflective layer thickness.

    摘要翻译： 本发明提供一种选择抗反射层厚度以在高K电介质层上图案化薄膜硅栅极层的方法。 该方法包括选择试验抗反射层厚度。 在光刻波长处计算从光致抗蚀剂层和抗反射层之间的界面反射的第一相干照明强度。 在光刻波长处计算从抗反射层和多晶硅层之间的界面反射的第二相干照明强度。 并且，在光刻波长处计算从多晶硅层和高K电介质层之间的界面反射的第三相干照明强度。 计算包括第一相干照明强度，第二相干照射强度和第三相干照明强度的总和的总相干照明强度并将其与预定阈值进行比较。 如果低于阈值，则选择防反射层厚度作为抗反射层厚度。

    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
    3.
    发明授权
    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
    具有高K电介质的半导体器件具有渐变介电常数的间隔物

    公开(公告)号：US06764966B1

    公开(公告)日：2004-07-20

    申请号：US10085278

    申请日：2002-02-27

    申请人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    发明人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    IPC分类号： H01L2128

    CPC分类号： H01L29/6656 ,  H01L29/66833 ,  H01L29/78

    摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

    摘要翻译： 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

    Silicon oxime spacer for preventing over-etching during local interconnect formation
    6.
    发明授权
    Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
    硅肟间隔物，用于在局部互连形成期间防止过蚀刻

    公开(公告)号：US5990524A

    公开(公告)日：1999-11-23

    申请号：US993868

    申请日：1997-12-18

    申请人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

    发明人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

    IPC分类号： H01L21/768 ,  H01L29/78

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.

    摘要翻译： 在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底， 更重叠的电介质层。 穿通区域可能会损坏晶体管电路。 提供改进的多用途间隔件以减少过度蚀刻的机会。 多用途间隔件由硅肟制成。 用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。 此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

    Treatment of dielectric material to enhance etch rate
    7.
    发明授权
    Treatment of dielectric material to enhance etch rate 有权
    处理电介质材料以提高蚀刻速率

    公开(公告)号：US06905971B1

    公开(公告)日：2005-06-14

    申请号：US10331938

    申请日：2002-12-30

    申请人： Cyrus Tabery ,  Chih-Yuh Yang ,  William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

    发明人： Cyrus Tabery ,  Chih-Yuh Yang ,  William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

    IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461

    CPC分类号： H01L21/31116 ,  H01L21/31122

    摘要： In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase removal rate of the one or more exposed portions upon etching; and (B) removing the one or more exposed portions of the dielectric layer in the same plasma etching tool of step (A) via plasma etching.

    摘要翻译： 在一个实施例中，本发明涉及一种用于在半导体器件中预处理和蚀刻电介质层的方法，包括以下步骤：（A）用等离子体中的等离子体预处理介电层的一个或多个暴露部分 蚀刻工具，以在蚀刻时增加一个或多个暴露部分的去除速率; 和（B）通过等离子体蚀刻在步骤（A）的相同等离子体蚀刻工具中去除介电层的一个或多个暴露部分。

    Silicon-starved PECVD method for metal gate electrode dielectric spacer
    9.
    发明授权
    Silicon-starved PECVD method for metal gate electrode dielectric spacer 失效
    用于金属栅极电介质间隔物的硅缺陷PECVD方法

    公开(公告)号：US06509282B1

    公开(公告)日：2003-01-21

    申请号：US09994128

    申请日：2001-11-26

    申请人： Minh Van Ngo ,  Arvind Halliyal

    发明人： Minh Van Ngo ,  Arvind Halliyal

    IPC分类号： H01L2131

    CPC分类号： H01L21/3145 ,  C23C16/308 ,  H01L21/28079 ,  H01L21/28088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making a semiconductor device including a metal gate electrode on a semiconductor substrate with a silicon oxynitride spacer formed on a surface of the metal gate electrode, wherein an interface of the silicon oxynitride spacer and the metal gate electrode is substantially free of metal silicide. The process includes steps of forming a metal gate electrode on a semiconductor substrate; forming by PECVD on a surface of the metal gate electrode a silicon oxynitride spacer, wherein the silicon oxynitride spacer is formed under initially silicon-starved conditions in which a first quantity of at least one silicon-containing material is provided to a PECVD apparatus which is reduced relative to an amount of at least one other reactant, as a result of which substantially no silicide is formed.

    摘要翻译： 一种在半导体衬底上制造半导体器件的方法，该半导体器件在金属栅电极的表面上形成有氧氮化硅间隔物，其中氧氮化硅间隔物和金属栅电极的界面基本上不含金属硅化物 。 该方法包括在半导体衬底上形成金属栅电极的步骤; 通过PECVD在金属栅电极的表面上形成氮氧化硅间隔物，其中在最初的硅饥饿条件下形成氮氧化硅间隔物，其中第一量的至少一种含硅材料被提供给PECVD装置，该PECVD装置是 相对于至少一种其它反应物的量减少，结果基本上没有形成硅化物。

    Semiconductor memory with data retention liner
    10.
    发明授权
    Semiconductor memory with data retention liner 有权
    具有数据保留衬垫的半导体存储器

    公开(公告)号：US07297592B1

    公开(公告)日：2007-11-20

    申请号：US11195201

    申请日：2005-08-01

    申请人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn Hopper ,  Pei-Yuan Gao

    发明人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn Hopper ,  Pei-Yuan Gao

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L21/3185 ,  H01L27/11568

    摘要： A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.

    摘要翻译： 一种用于双位闪速存储器的制造方法包括提供半导体衬底和沉积电荷捕获电介质层，其中沉积是以超低沉积速率使用氨而不使用氨。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 减少氢，高密度数据保持衬垫以减少电荷损失，覆盖字线和电荷捕获电介质层。 层间绝缘层沉积在数据保持衬里上。