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    System and method for controlling overshoot and undershoot in a switching regulator
    2.
    发明授权
    System and method for controlling overshoot and undershoot in a switching regulator 有权
    用于控制开关调节器中的过冲和下冲的系统和方法

    公开(公告)号：US07982445B1

    公开(公告)日：2011-07-19

    申请号：US11983352

    申请日：2007-11-08

    申请人： Jane Xin-LeBlanc

    发明人： Jane Xin-LeBlanc

    IPC分类号： G05F1/40

    CPC分类号： H02M3/158 ,  H02M2001/0045

    摘要： A system and a method are disclosed for controlling overshoot and undershoot in a switching regulator circuit. A first comparator circuit for controlling an undershoot of an output voltage of the switching regulator circuit is provided that that detects an occurrence of an undershoot of the output voltage of the switching regulator circuit and activates a first current source to pull up the output voltage of the switching regulator circuit. A second comparator circuit for controlling an overshoot of an output voltage of the switching regulator circuit is provided that detects an occurrence of an overshoot of the output voltage of the switching regulator circuit and activates a second current source to pull down the output voltage of the switching regulator circuit.

    摘要翻译： 公开了一种用于控制开关调节器电路中的过冲和下冲的系统和方法。 提供了一种用于控制开关调节器电路的输出电压的下冲的第一比较器电路，其用于检测开关调节器电路的输出电压的下冲的发生，并激活第一电流源以提升开关稳压器的输出电压 开关稳压电路。 提供了用于控制开关调节器电路的输出电压的过冲的第二比较器电路，其检测开关调节器电路的输出电压的过冲的发生，并激活第二电流源以将开关的输出电压下拉 调节电路。

    Low power differential-to-single-ended converter with good duty cycle performance
    3.
    发明授权
    Low power differential-to-single-ended converter with good duty cycle performance 有权
    低功耗差分到单端转换器具有良好的占空比性能

    公开(公告)号：US07061277B1

    公开(公告)日：2006-06-13

    申请号：US10972744

    申请日：2004-10-25

    申请人： Jane Xin-LeBlanc

    发明人： Jane Xin-LeBlanc

    IPC分类号： H03K9/08

    CPC分类号： H03K5/13 ,  H03K3/017 ,  H03K3/033 ,  H03K3/037 ,  H03K5/1565 ,  H03L7/0995 ,  H03L7/1974

    摘要： A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.

    摘要翻译： 差分至单端（DSE）转换器接收正差分输入和负差分输入，并生成单端输出。 DSE转换器包括：1）具有耦合到正差分输入的非反相输入和耦合到负差分输入的反相输入的第一比较器; 2）具有耦合到所述正差分输入的反相输入和耦合到所述负差分输入的非反相输入的第二比较器; 3）具有逻辑1输入并由第一比较器输出上的上升沿计时的第一D触发器; 4）具有逻辑1输入并由第二比较器输出上的上升沿计时的第二D触发器; 以及5）锁存电路，其具有耦合到所述第一D触发器输出的第一输入和耦合到所述第二D触发器输出的第二输入。 第一和第二D触发器输出端的上升沿导致锁存器输出改变状态。

    Low power differential-to-single-ended converter with good duty cycle performance
    4.
    发明授权
    Low power differential-to-single-ended converter with good duty cycle performance 有权
    低功耗差分到单端转换器具有良好的占空比性能

    公开(公告)号：US06809566B1

    公开(公告)日：2004-10-26

    申请号：US10630153

    申请日：2003-07-30

    申请人： Jane Xin-LeBlanc

    发明人： Jane Xin-LeBlanc

    IPC分类号： H03L706

    CPC分类号： H03K5/13 ,  H03K3/017 ,  H03K3/033 ,  H03K3/037 ,  H03K5/1565 ,  H03L7/0995 ,  H03L7/1974

    摘要： A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.

    摘要翻译： 差分至单端（DSE）转换器接收正差分输入和负差分输入，并生成单端输出。 DSE转换器包括：1）具有耦合到正差分输入的非反相输入和耦合到负差分输入的反相输入的第一比较器; 2）具有耦合到所述正差分输入的反相输入和耦合到所述负差分输入的非反相输入的第二比较器; 3）具有逻辑1输入并由第一比较器输出上的上升沿计时的第一D触发器; 4）具有逻辑1输入并由第二比较器输出上的上升沿计时的第二D触发器; 以及5）锁存电路，其具有耦合到所述第一D触发器输出的第一输入和耦合到所述第二D触发器输出的第二输入。 第一和第二D触发器输出端的上升沿导致锁存器输出改变状态。

    UNIVERSAL TWO-INPUT LOGIC GATE THAT IS CONFIGURABLE AND CONNECTABLE IN AN INTEGRATED CIRCUIT BY A SINGLE MASK LAYER ADJUSTMENT
    5.
    发明申请
    UNIVERSAL TWO-INPUT LOGIC GATE THAT IS CONFIGURABLE AND CONNECTABLE IN AN INTEGRATED CIRCUIT BY A SINGLE MASK LAYER ADJUSTMENT 有权
    通用单面掩模调整在通用集成电路中可配置和连接的通用双输入逻辑门

    公开(公告)号：US20100301901A1

    公开(公告)日：2010-12-02

    申请号：US12853488

    申请日：2010-08-10

    申请人： Jane Xin-LeBlanc

    发明人： Jane Xin-LeBlanc

    IPC分类号： H03K19/00

    CPC分类号： H01L27/11807 ,  H01L27/0207

    摘要： A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit.

    摘要翻译： 用于实现多个逻辑门中的任何一个逻辑门的备用逻辑电路包括多路复用器电路，其选择输入用作逻辑门输入，并且其输出用作逻辑门输出。 复用器电路的多个数据输入中的每一个被配置为接收定义所需逻辑功能的第一和第二逻辑电压电平之一。 通过修改单个光刻掩模，备用逻辑门可以：配置为执行所需的逻辑功能; 连接到目标逻辑电路; 或者被配置并连接到目标逻辑电路中。

    Circuits for reducing leakage currents in pull-up and pull-down circuits using very small MOSFET devices
    6.
    发明授权
    Circuits for reducing leakage currents in pull-up and pull-down circuits using very small MOSFET devices 有权
    使用非常小的MOSFET器件减少上拉和下拉电路中的漏电流的电路

    公开(公告)号：US06859083B1

    公开(公告)日：2005-02-22

    申请号：US10630322

    申请日：2003-07-30

    申请人： Jane Xin-LeBlanc ,  Wai Lau

    发明人： Jane Xin-LeBlanc ,  Wai Lau

    IPC分类号： H03L7/089 ,  H03L5/00

    CPC分类号： H03L7/0891

    摘要： A pull-down circuit for pulling a high-impedance node to ground when a pull-down (PD) signal driving the pull-down circuit is Logic 1. The pull-down circuit comprises: 1) a first pull-down N-channel transistor having a drain coupled to the high-impedance node, a gate coupled to the PD signal, and a source coupled to a common node; 2) a second pull-down N-channel transistor having a drain coupled to the common node, a gate coupled to the PD signal, and a source coupled to a ground rail;, wherein the first and second pull-down N-channel transistors are off when the PD signal is Logic 0 and are on when the PD signal is Logic 1; and 3) a gate-biasing circuit driven by the PD signal. The gate-biasing circuit is off when the PD signal is Logic 1 and the gate-biasing circuit applies a Logic 1 bias voltage to the common node when the PD signal is Logic 0. The Logic 1 bias voltage creates a negative Vgs bias on the first pull-down N-channel transistor when the PD signal is Logic 0. An analogous pull-up circuit also is disclosed.

    摘要翻译： 当驱动下拉电路的下拉（PD）信号是逻辑1时，用于将高阻抗节点拉到地的下拉电路。下拉电路包括：1）第一下拉N沟道 晶体管具有耦合到高阻抗节点的漏极，耦合到PD信号的栅极和耦合到公共节点的源极; 2）具有耦合到所述公共节点的漏极的第二下拉N沟道晶体管，耦合到所述PD信号的栅极和耦合到接地轨的源极;其中所述第一和第二下拉N沟道晶体管 当PD信号为逻辑0时为OFF，当PD信号为逻辑1时为ON; 和3）由PD信号驱动的栅极偏置电路。 当PD信号为逻辑1时，栅极偏置电路关闭，当PD信号为逻辑0时，栅极偏置电路向公共节点施加逻辑1偏置电压。逻辑1偏置电压在 当PD信号为逻辑0时，第一下拉式N沟道晶体管也是公开了类似的上拉电路。

    Saturation compensating analog to digital converter
    7.
    发明授权
    Saturation compensating analog to digital converter 有权
    饱和补偿模数转换器

    公开(公告)号：US06459397B1

    公开(公告)日：2002-10-01

    申请号：US09675987

    申请日：2000-09-29

    申请人： Christian Volf Olgaard ,  Jane Xin-LeBlanc

    发明人： Christian Volf Olgaard ,  Jane Xin-LeBlanc

    IPC分类号： H03M302

    CPC分类号： H03M3/486 ,  H03M3/40 ,  H03M3/43 ,  H03M3/438 ,  H03M3/49

    摘要： The saturation compensating analog to digital converter has converter circuitry receiving an analog signal and outputting converted data. The converted data from the converter circuitry is processed and filtered to provide a digital data output. The digital data output is received into shift register circuitry before being transmitted for later-stage processing. When the converter circuitry is operating close to a saturated condition, a saturation detector generates a saturation signal. The saturation signal is received at a variable gain circuit which adjusts the gain of the input signal to the converter circuitry. The shift register circuitry also receives the saturation signal and provides an upshift of the digital data to compensate for the associated reduction in input gain provided by the variable gain circuit. In operation, the variable gain circuit is initially set to its maximum output, thus providing the maximum possible input signal to the converter. If a near-saturation conditional is detected, the variable gain circuit is stepped down, and the shift register circuitry provides an associated one bit step up. Such saturation compensation is continued to enable the converter circuitry to operate without saturating.

    摘要翻译： 饱和补偿模数转换器具有接收模拟信号并输出​​转换数据的转换器电路。 来自转换器电路的经转换的数据被处理和滤波以提供数字数据输出。 数字数据输出在发送用于后期处理之前被接收到移位寄存器电路中。 当转换器电路工作在接近饱和状态时，饱和检测器产生饱和信号。 在可变增益电路处接收饱和信号，该可变增益电路调节到转换器电路的输入信号的增益。 移位寄存器电路还接收饱和信号并且提供数字数据的升档以补偿由可变增益电路提供的输入增益的相关联的降低。 在操作中，可变增益电路初始设置为其最大输出，从而为转换器提供最大可能的输入信号。 如果检测到近饱和条件，则可变增益电路被降低，并且移位寄存器电路提供相关的一位加法。 继续这种饱和补偿，使得转换器电路能够在没有饱和的情况下运行。

    Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment
    8.
    发明授权
    Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment 有权
    可通过单个掩模层调整在集成电路中配置和连接的通用双输入逻辑门

    公开(公告)号：US08423919B2

    公开(公告)日：2013-04-16

    申请号：US12853488

    申请日：2010-08-10

    申请人： Jane Xin-LeBlanc

    发明人： Jane Xin-LeBlanc

    IPC分类号： G06F17/50

    CPC分类号： H01L27/11807 ,  H01L27/0207

    摘要： A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit.

    摘要翻译： 用于实现多个逻辑门中的任何一个逻辑门的备用逻辑电路包括多路复用器电路，其选择输入用作逻辑门输入，并且其输出用作逻辑门输出。 复用器电路的多个数据输入中的每一个被配置为接收定义所需逻辑功能的第一和第二逻辑电压电平之一。 通过修改单个光刻掩模，备用逻辑门可以：配置为执行所需的逻辑功能; 连接到目标逻辑电路; 或者被配置并连接到目标逻辑电路中。

    Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment
    9.
    发明授权
    Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment 有权
    可通过单个掩模层调整在集成电路中配置和连接的通用双输入逻辑门

    公开(公告)号：US07805701B1

    公开(公告)日：2010-09-28

    申请号：US11005949

    申请日：2004-12-07

    申请人： Jane Xin-LeBlanc

    发明人： Jane Xin-LeBlanc

    IPC分类号： G06F17/50

    CPC分类号： H01L27/11807 ,  H01L27/0207

    摘要： A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit.

    摘要翻译： 用于实现多个逻辑门中的任何一个逻辑门的备用逻辑电路包括多路复用器电路，其选择输入用作逻辑门输入，并且其输出用作逻辑门输出。 复用器电路的多个数据输入中的每一个被配置为接收定义所需逻辑功能的第一和第二逻辑电压电平之一。 通过修改单个光刻掩模，备用逻辑门可以：配置为执行所需的逻辑功能; 连接到目标逻辑电路; 或者被配置并连接到目标逻辑电路中。

    Apparatus and method for transparent dynamic range scaling for open loop LED drivers
    10.
    发明授权
    Apparatus and method for transparent dynamic range scaling for open loop LED drivers 有权
    用于开环LED驱动器的透明动态范围缩放的装置和方法

    公开(公告)号：US06972530B1

    公开(公告)日：2005-12-06

    申请号：US10818237

    申请日：2004-04-05

    申请人： Jane Xin-LeBlanc

    发明人： Jane Xin-LeBlanc

    IPC分类号： G05F1/00 ,  H05B33/08 ,  H05B37/02

    CPC分类号： H05B33/0815 ,  H05B33/0848

    摘要： The dynamic range of a charging current in an open-loop LED driver circuit is scaled to provide a charging current within tolerance for the open-loop LED driver. The scaling of the dynamic range of the charging current is performed transparently to the user, such that user selected parameters for the open-loop LED driver remain unchanged during circuit performance.

    摘要翻译： 开环LED驱动器电路中的充电电流的动态范围被缩放以提供对于开环LED驱动器的容限内的充电电流。 充电电流的动态范围的缩放对用户透明地执行，使得用户选择的开环LED驱动器的参数在电路性能期间保持不变。