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公开(公告)号：US4647957A
公开(公告)日：1987-03-03
申请号：US857392
申请日：1986-04-21
IPC分类号： H01L21/763 , H01L27/092 , H01L27/02 , H01L29/06
CPC分类号： H01L27/0921 , H01L21/763
摘要： A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.
摘要翻译： 公开了一种新的CMOS器件，其避免了在小于10μm的器件的n沟道FET和p沟道FET之间实现间隔而闭锁，以及制造该选择的方法。 本发明的器件，其形成在包括相对重掺杂的体区域的衬底中，该衬底包括相对较薄的适中掺杂层，其包括延伸穿过层的一部分的多晶硅填充沟槽，其中n沟道FET和p沟道FET之间 装置。 本发明的器件还包括从沟槽的底部延伸到体区的相对重掺杂的区域。 掺杂多晶硅的沟槽与相对重掺杂的区域和体区两者结合防止闭锁。
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公开(公告)号：US4646123A
公开(公告)日：1987-02-24
申请号：US857391
申请日：1986-04-21
IPC分类号： H01L21/763 , H01L27/092 , H01L27/02 , H01L29/06
CPC分类号： H01L27/0921 , H01L21/763
摘要： A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the device, is disclosed.The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10 .mu.m, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.
摘要翻译： 公开了一种新的CMOS器件，其避免了在小于10μm的器件的n沟道FET和p沟道FET之间实现间隔而闭锁，以及制造器件的方法。 本发明的CMOS器件包括形成在器件的n沟道FET和p沟道FET之间的半导体衬底中的防止闭锁的多晶硅填充沟槽。 多晶硅填充的沟槽基本上没有引起裂纹的空隙，并且达到宽度小于10微米，因为沟槽侧壁和垂直于衬底表面的垂线之间的角度大于或等于约5度 但小于约10度。 此外，沉积到沟槽中的多晶硅的厚度大于沟槽宽度的一半。
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公开(公告)号：US4766090A
公开(公告)日：1988-08-23
申请号：US933631
申请日：1986-11-21
IPC分类号： H01L21/763 , H01L21/425
CPC分类号： H01L21/763
摘要： A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed.The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.
摘要翻译： 公开了一种新的CMOS器件，其避免了在小于10μm的器件的n沟道FET和p沟道FET之间实现间隔而闭锁，以及制造该选择的方法。 本发明的器件，其形成在包括相对重掺杂的体区域的衬底中，该衬底包括相对较薄的适中掺杂层，其包括延伸穿过层的一部分的多晶硅填充沟槽，其中n沟道FET和p沟道FET之间 装置。 本发明的器件还包括从沟槽的底部延伸到体区的相对重掺杂的区域。 掺杂多晶硅的沟槽与相对重掺杂的区域和体区两者结合防止闭锁。
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公开(公告)号：US4656730A
公开(公告)日：1987-04-14
申请号：US674274
申请日：1984-11-23
IPC分类号： H01L21/76 , H01L21/033 , H01L21/225 , H01L21/762 , H01L21/763 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78 , H01L21/38 , H01L21/461
CPC分类号： H01L21/76232 , H01L21/033 , H01L21/2253 , H01L21/76202 , H01L21/763 , H01L21/823892 , H01L27/0921 , Y10S438/938
摘要： A new method for fabricating CMOS devices, as well as the resulting devices, is disclosed. The method involves incorporating dopants into a semiconductor substrate through a region of the substrate surface, and diffusing the implanted dopants into the substrate to form a tub. Prior to the diffusion step, a trench is formed in, and extending beneath, the surface which partially or completely encircles the region. The trench serves to prevent the formation, or reduce the size, of a relatively low dopant concentration region, which would otherwise lead to undesirable leakage currents in the completed CMOS device, and prevents latchup.
摘要翻译： 公开了一种用于制造CMOS器件的新方法以及所得到的器件。 该方法包括通过衬底表面的区域将掺杂剂掺入到半导体衬底中，以及将注入的掺杂剂扩散到衬底中以形成桶。 在扩散步骤之前，在部分地或完全地环绕该区域的表面上形成沟槽并在其下方延伸。 该沟槽用于防止相对低的掺杂剂浓度区域的形成或减小尺寸，否则这将导致完成的CMOS器件中的不期望的泄漏电流，并且防止闭锁。
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公开(公告)号：US4951100A
公开(公告)日：1990-08-21
申请号：US374703
申请日：1989-07-03
申请人： Louis C. Parrillo
发明人： Louis C. Parrillo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/417 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/0603 , H01L29/41775 , H01L29/6656 , H01L29/78 , Y10S257/90
摘要： A lightly-doped drain (LDD) structure has conductive shield overlying the lightly-doped drain and source portions to collect and/or remove hot carriers which can otherwise cause instabilities such as gain degradation and threshold voltage shifts in short-channel MOS devices. The hot carriers eventually deteriorate the performance of the transistor to the point where the transistor provides insufficient performance. Thus, the lifetime of a transistor is affected by the degradation caused by the formation of hot carriers. The lifetime is increased by collecting the hot carriers in the conductive material over the lightly-doped source and drain.
摘要翻译： 轻掺杂漏极（LDD）结构具有覆盖轻掺杂漏极和源极部分的导电屏蔽以收集和/或去除热载流子，否则可能引起短路MOS器件中的增益劣化和阈值电压偏移等不稳定性。 热载流子最终将晶体管的性能恶化到晶体管提供不足的性能。 因此，晶体管的寿命受热载流子形成所引起的劣化的影响。 通过在轻掺杂的源极和漏极上收集导电材料中的热载流子来增加寿命。
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公开(公告)号：US4929565A
公开(公告)日：1990-05-29
申请号：US429953
申请日：1989-10-30
申请人： Louis C. Parrillo
发明人： Louis C. Parrillo
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823892 , H01L27/0928 , Y10S438/975
摘要： A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.
摘要翻译： 一种用于在半导体衬底中形成n阱和p阱的工艺，其中每个阱具有浅的，高度掺杂的表面层，其深度可以独立控制。 双阱CMOS工艺的这种高/低掺杂分布可以仅使用一个掩模级来产生。 该方法在每个阱中提供高/低杂质分布，以优化NMOS和PMOS有源晶体管; 提供关闭NMOS至PMOS晶体管间距; 避免通道停止掩码级别，并避免阈值调整/穿透掩码级别。
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公开(公告)号：US10448763B2
公开(公告)日：2019-10-22
申请号：US15377277
申请日：2016-12-13
申请人： Louis C. Parrillo
发明人： Louis C. Parrillo
摘要： Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.
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公开(公告)号：US09549624B2
公开(公告)日：2017-01-24
申请号：US14859413
申请日：2015-09-21
申请人： Louis C. Parrillo
发明人： Louis C. Parrillo
摘要： Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.
摘要翻译： 本文公开的实施例描述了用于悬挂装置的系统和方法，其包括滑动构件，用于将悬挂装置与框架和墙壁对准所需位置。 实施例可以被配置为在水平和垂直方向上与框架对齐。
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9.发明授权Process for fabricating a semiconductor device having an improved metal interconnect structure 失效具有改进的金属互连结构的半导体器件的制造方法
公开(公告)号：US5527739A
公开(公告)日：1996-06-18
申请号：US448157
申请日：1995-05-23
IPC分类号： H01L23/522 , H01L23/532 , H01L21/28
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , Y10S438/927
摘要： A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).
摘要翻译： 金属互连结构包括位于耐火金属通孔塞（28）和第一和第二金属互连层（16,32）之间的铜界面层（24,30）。 铜界面层（24,30）被限制在覆盖在第一互连层（16）上并包含通孔塞（28）的绝缘层（20）中的通路孔（22）的区域中。 对界面层（24,30）进行退火处理，以在与界面层（24,30）相邻的互连层（16,32）中提供铜储存器（36,37）。 当电流通过互连结构时，铜储存器（36,37）连续补充从界面耗尽的铜。 一种方法包括将铜选择性沉积在第一金属互连层（16）的暴露区域（23）上，并在上部通孔塞（28）上，然后在形成气体中进行退火以形成铜储存器 36,37）。
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公开(公告)号：US4808555A
公开(公告)日：1989-02-28
申请号：US884113
申请日：1986-07-10
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L29/66575
摘要： A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process versatility in incorporating implantation steps and patterning steps between formation of the thin layers of conductive material. Direct transfer from dielectric layer formation to conductive material layer formation steps, and performing the intermediate process steps in the same piece of equipment as the thin conductive layer formation assists in adhesion of the thin layers to each other to form the total conductive material layer. The use of in situ doped semiconductor material, such as in situ doped polycrystalline silicon and in situ doped amorphous silicon reduces the exposure of other dopants that may be present to thermal cycles of high temperature, greater than 900.degree. C., that causes these dopants to migrate undesirably.
摘要翻译： 一种通过从多个导电材料薄层形成导电材料层，至少在两个步骤中形成导电材料层的工艺。 导电材料层的两步形成方法的使用允许在形成导电材料的薄层之间的植入步骤和图案化步骤中的工艺通用性。 从介电层形成到导电材料层形成步骤的直接转移，以及执行与薄导电层形成相同的设备中的中间工艺步骤有助于薄层彼此粘附以形成总导电材料层。 使用原位掺杂的半导体材料，例如原位掺杂的多晶硅和原位掺杂的非晶硅，可以降低可能存在于高于900℃的热循环的其他掺杂剂的暴露，导致这些掺杂剂 不期望地迁移。
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