公开(公告)号：US4951100A

公开(公告)日：1990-08-21

申请号：US374703

申请日：1989-07-03

申请人： Louis C. Parrillo

发明人： Louis C. Parrillo

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/0603 ,  H01L29/41775 ,  H01L29/6656 ,  H01L29/78 ,  Y10S257/90

摘要： A lightly-doped drain (LDD) structure has conductive shield overlying the lightly-doped drain and source portions to collect and/or remove hot carriers which can otherwise cause instabilities such as gain degradation and threshold voltage shifts in short-channel MOS devices. The hot carriers eventually deteriorate the performance of the transistor to the point where the transistor provides insufficient performance. Thus, the lifetime of a transistor is affected by the degradation caused by the formation of hot carriers. The lifetime is increased by collecting the hot carriers in the conductive material over the lightly-doped source and drain.

摘要翻译： 轻掺杂漏极（LDD）结构具有覆盖轻掺杂漏极和源极部分的导电屏蔽以收集和/或去除热载流子，否则可能引起短路MOS器件中的增益劣化和阈值电压偏移等不稳定性。 热载流子最终将晶体管的性能恶化到晶体管提供不足的性能。 因此，晶体管的寿命受热载流子形成所引起的劣化的影响。 通过在轻掺杂的源极和漏极上收集导电材料中的热载流子来增加寿命。

公开(公告)号：US4929565A

公开(公告)日：1990-05-29

申请号：US429953

申请日：1989-10-30

申请人： Louis C. Parrillo

发明人： Louis C. Parrillo

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823892 ,  H01L27/0928 ,  Y10S438/975

摘要： A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.

摘要翻译： 一种用于在半导体衬底中形成n阱和p阱的工艺，其中每个阱具有浅的，高度掺杂的表面层，其深度可以独立控制。 双阱CMOS工艺的这种高/低掺杂分布可以仅使用一个掩模级来产生。 该方法在每个阱中提供高/低杂质分布，以优化NMOS和PMOS有源晶体管; 提供关闭NMOS至PMOS晶体管间距; 避免通道停止掩码级别，并避免阈值调整/穿透掩码级别。

公开(公告)号：US10448763B2

公开(公告)日：2019-10-22

申请号：US15377277

申请日：2016-12-13

申请人： Louis C. Parrillo

发明人： Louis C. Parrillo

IPC分类号： F16M13/00 ,  A47G1/20 ,  G01C9/34

摘要： Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.

公开(公告)号：US09549624B2

公开(公告)日：2017-01-24

申请号：US14859413

申请日：2015-09-21

申请人： Louis C. Parrillo

发明人： Louis C. Parrillo

IPC分类号： F16M13/00 ,  A47G1/20

CPC分类号： A47G1/205 ,  A47G1/20 ,  G01C9/34

摘要： Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.

摘要翻译： 本文公开的实施例描述了用于悬挂装置的系统和方法，其包括滑动构件，用于将悬挂装置与框架和墙壁对准所需位置。 实施例可以被配置为在水平和垂直方向上与框架对齐。

公开(公告)号：US5527739A

公开(公告)日：1996-06-18

申请号：US448157

申请日：1995-05-23

申请人： Louis C. Parrillo ,  Jeffrey L. Klein

发明人： Louis C. Parrillo ,  Jeffrey L. Klein

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/28

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L23/53219 ,  H01L2924/0002 ,  Y10S438/927

摘要： A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).

摘要翻译： 金属互连结构包括位于耐火金属通孔塞（28）和第一和第二金属互连层（16,32）之间的铜界面层（24,30）。 铜界面层（24,30）被限制在覆盖在第一互连层（16）上并包含通孔塞（28）的绝缘层（20）中的通路孔（22）的区域中。 对界面层（24,30）进行退火处理，以在与界面层（24,30）相邻的互连层（16,32）中提供铜储存器（36,37）。 当电流通过互连结构时，铜储存器（36,37）连续补充从界面耗尽的铜。 一种方法包括将铜选择性沉积在第一金属互连层（16）的暴露区域（23）上，并在上部通孔塞（28）上，然后在形成气体中进行退火以形成铜储存器 36,37）。

公开(公告)号：US4808555A

公开(公告)日：1989-02-28

申请号：US884113

申请日：1986-07-10

申请人： Richard W. Mauntel ,  Stephen J. Cosentino ,  Louis C. Parrillo ,  Patrick J. Holly

发明人： Richard W. Mauntel ,  Stephen J. Cosentino ,  Louis C. Parrillo ,  Patrick J. Holly

IPC分类号： H01L21/336 ,  H01L21/283

CPC分类号： H01L29/66575

摘要： A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process versatility in incorporating implantation steps and patterning steps between formation of the thin layers of conductive material. Direct transfer from dielectric layer formation to conductive material layer formation steps, and performing the intermediate process steps in the same piece of equipment as the thin conductive layer formation assists in adhesion of the thin layers to each other to form the total conductive material layer. The use of in situ doped semiconductor material, such as in situ doped polycrystalline silicon and in situ doped amorphous silicon reduces the exposure of other dopants that may be present to thermal cycles of high temperature, greater than 900.degree. C., that causes these dopants to migrate undesirably.

摘要翻译： 一种通过从多个导电材料薄层形成导电材料层，至少在两个步骤中形成导电材料层的工艺。 导电材料层的两步形成方法的使用允许在形成导电材料的薄层之间的植入步骤和图案化步骤中的工艺通用性。 从介电层形成到导电材料层形成步骤的直接转移，以及执行与薄导电层形成相同的设备中的中间工艺步骤有助于薄层彼此粘附以形成总导电材料层。 使用原位掺杂的半导体材料，例如原位掺杂的多晶硅和原位掺杂的非晶硅，可以降低可能存在于高于900℃的热循环的其他掺杂剂的暴露，导致这些掺杂剂 不期望地迁移。

公开(公告)号：US4808543A

公开(公告)日：1989-02-28

申请号：US860734

申请日：1986-05-07

申请人： Louis C. Parrillo ,  Richard W. Mauntel ,  John M. Barden

发明人： Louis C. Parrillo ,  Richard W. Mauntel ,  John M. Barden

IPC分类号： H01L21/225 ,  H01L21/266 ,  H01L21/334 ,  H01L29/94 ,  H01L29/92

CPC分类号： H01L29/66181 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/945

摘要： A bulge well structure for trench devices in wells of a conductivity type opposite to that of the substrate where the bottom of the trench has localized, extra doping. The additional doping into the bottom of the trench prior to device formation may be implanted while the photoresist mask for the trench formation is still in place. In one embodiment of the method, the trenches and the bulge or well extension formations at their bottoms are created before isolation regions are formed. The structure and method permit increased doping only where needed and are compatible with thin epitaxial layers and sharp transition interfaces of epitaxy with substrate for optimum latchup protection. No extra masks are required and the tight packing allowed by trench technology is not altered. Protection against soft errors and junction leakage by forming DRAM trench capacitors in a well of opposite conductivity type from the substrate may be provided.

摘要翻译： 具有导电类型的阱中的沟槽器件的凸起阱结构，其与衬底的底部相反，其中沟槽的底部具有局部化，额外的掺杂。 在器件形成之前在沟槽底部的额外掺杂可以被注入，而用于沟槽形成的光致抗蚀剂掩模仍然在位。 在该方法的一个实施方案中，在形成隔离区之前，在其底部产生沟槽和凸起或阱延伸构造。 该结构和方法允许仅在需要时增加掺杂，并且与薄的外延层和外延与衬底的尖锐过渡界面相适应以实现最佳的闭锁保护。 不需要额外的掩模，沟槽技术允许的紧密包装不会改变。 可以提供通过在与衬底相反的导电类型的阱中形成DRAM沟槽电容器来防止软错误和结漏电的保护。

公开(公告)号：US4769747A

公开(公告)日：1988-09-06

申请号：US36758

申请日：1987-04-08

申请人： Louis C. Parrillo

发明人： Louis C. Parrillo

IPC分类号： B23D33/12 ,  B26D7/01 ,  G03D15/04 ,  F21V33/00

CPC分类号： B26D7/015 ,  B23D33/12 ,  G03D15/043 ,  B26D2007/0087 ,  Y10T83/828

摘要： An illuminated paper cutter comprising an opaque cutting board having a cutting edge at one side, a cutting blade pivotally attached to the cutting board to coact with the cutting edge to cut material placed between the cutting blade and the cutting edge, and an illuminator attached to the cutting board to illuminate the cutting edge from below, the illuminator being located so as to not extend beyond the outside edge of the cutting edge.

摘要翻译： 一种照明式切纸机，包括在一侧具有切割边缘的不透明切割板，可旋转地附接到切割板以与切割边缘共同切割放置在切割刀片和切割边缘之间的切割材料的切割刀片，以及附接到 切割板从下方照亮切割边缘，照明器被定位成不延伸超过切割边缘的外边缘。

公开(公告)号：US4745086A

公开(公告)日：1988-05-17

申请号：US47589

申请日：1987-05-11

申请人： Louis C. Parrillo ,  Stephen J. Cosentino ,  Richard W. Mauntel

发明人： Louis C. Parrillo ,  Stephen J. Cosentino ,  Richard W. Mauntel

IPC分类号： H01L21/033 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L21/26 ,  H01L21/265 ,  H01L21/22

CPC分类号： H01L29/6653 ,  H01L21/0337 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/78 ,  Y10S148/082 ,  Y10S148/106 ,  Y10S148/116 ,  Y10S257/90

摘要： A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

摘要翻译： 一种使用可移除的侧壁间隔物的方法，以最小化在形成CMOS集成电路时形成轻掺杂的漏极（LDD）中的掩模电平的需要。 铝或化学气相沉积（CVD）金属如钨是合适的材料，用于在重掺杂的源极/漏极区域注入期间形成存在于CMOS栅极周围的可移除的侧壁间隔物。 诸如CVD多晶硅的其它材料也可用于侧壁间隔物。 在栅极周围的轻掺杂漏极区域注入之前去除侧壁间隔物。 这种植入序列正好与当前对轻掺杂漏极形成实践相反。 本发明还包括使用差示氧化物层。 第二组一次性侧壁间隔件或永久侧壁间隔件的使用形成可选实施例。

公开(公告)号：US4717683A

公开(公告)日：1988-01-05

申请号：US910927

申请日：1986-09-23

申请人： Louis C. Parrillo ,  Stephen J. Cosentino ,  Bridgette A. Bergami

发明人： Louis C. Parrillo ,  Stephen J. Cosentino ,  Bridgette A. Bergami

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/823807 ,  H01L21/76218 ,  H01L27/0928

摘要： A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask. A first N-type implant is performed at energy sufficient to penetrate through the first mask but insufficient to penetrate through the fourth mask. This implant provides punch through protection for P channel transistors to be formed later. A second N-type impurity is implanted into the surface at an implant energy insufficient to penetrate through the first mask to provided field doping. The silicon substrate is then oxidized to form a field oxide at portions of the first and second surface regions which are not covered by the first and second masks.

摘要翻译： 公开了一种制造互补绝缘栅场效应晶体管的方法，其包括掺杂场隔离区和可选的穿通保护。 在本发明的一个实施例中，提供了具有N型和P型表面区域的硅衬底。 形成覆盖两个表面区域的有效区域的第一和第二掩模。 然后形成覆盖第一区域和第一掩模的第三掩模。 P型杂质以足以穿透第二掩模但不能透过第三掩模的注入能量注入第二区域。 以不足以穿过任一掩模的植入能量来执行第二P型植入物。 第一种植入物将有助于防止穿透，而第二种植入物则会涂覆场区域。 然后形成覆盖第二区域和第二掩模的第四掩模。 以足以穿透第一掩模但不足以穿透第四掩模的能量进行第一N型植入物。 该种植体为稍后形成的P沟道晶体管提供穿通保护。 以不足以穿透第一掩模的注入能量将第二N型杂质注入表面，以提供场掺杂。 然后在不被第一和第二掩模覆盖的第一表面区域和第二表面区域的部分处，氧化硅衬底以形成场氧化物。