公开(公告)号：US09123567B2

公开(公告)日：2015-09-01

申请号：US13976411

申请日：2011-12-19

申请人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

发明人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/78

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

摘要翻译： 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够为给定的布局区域提供显着的驱动电流。

公开(公告)号：US08633471B2

公开(公告)日：2014-01-21

申请号：US13032777

申请日：2011-02-23

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L29/12

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include a modulation doped heterostructure, wherein the modulation doped heterostructure may comprise an active portion having a first bandgap and a delta doped portion having a second bandgap.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例，其可以包括调制掺杂异质结构，其中调制掺杂异质结构可以包括具有第一带隙的有源部分和具有第二带隙的δ掺杂部分。

公开(公告)号：US07915642B2

公开(公告)日：2011-03-29

申请号：US12319097

申请日：2008-12-30

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L29/778

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20090315101A1

公开(公告)日：2009-12-24

申请号：US12145020

申请日：2008-06-24

申请人： Willy Rachmady ,  Jack Kavalieros

发明人： Willy Rachmady ,  Jack Kavalieros

IPC分类号： H01L29/78 ,  H01L21/764

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.

摘要翻译： 形成用于非平面晶体管的缺口基隔离物轮廓的方法包括提供在衬底上具有通道区域的半导体鳍片，并且形成与沟道区域的侧壁相邻并且在沟道区域的顶表面上的栅电极， 栅电极在顶表面上具有硬掩模。 使用增强的化学气相沉积（PE-CVD）工艺在栅极和散热片上沉积间隔层。 将多蚀刻工艺应用于间隔层，以在栅电极的横向相对侧上形成一对凹口，其中每个凹口位于翅片的侧壁和鳍的顶表面附近。

公开(公告)号：US20090085169A1

公开(公告)日：2009-04-02

申请号：US11864899

申请日：2007-09-28

申请人： Willy Rachmady ,  Brian S. Doyle ,  Jack Kavalieros ,  Rajwinder Singh

发明人： Willy Rachmady ,  Brian S. Doyle ,  Jack Kavalieros ,  Rajwinder Singh

IPC分类号： H01L21/461 ,  H01L29/06

CPC分类号： H01L29/66181 ,  H01L21/3065 ,  H01L29/66795

摘要： A high aspect ratio silicon structure comprises a silicon substrate (110) having a surface (111), an electrically insulating layer (120) over portions of the silicon substrate, a hardmask (130) over the electrically insulating layer, and a deep silicon trench (140) formed in the substrate. The deep silicon trench comprises a floor (141) and sidewalls (142) extending away from the floor, and the sidewalls are atomically smooth. In an embodiment, the atomically smooth sidewalls are achieved by providing a substrate having the deep silicon trench formed therein, forming a layer of water over the substrate and within the deep silicon trench, and exposing the substrate to a hydrogen fluoride vapor and to an ozone gas.

摘要翻译： 高纵横比硅结构包括具有表面（111）的硅衬底（110），硅衬底的部分上的电绝缘层（120），电绝缘层上的硬掩模（130）和深硅沟槽 （140）。 深硅沟槽包括从地板延伸的地板（141）和侧壁（142），并且侧壁是原子平滑的。 在一个实施例中，通过提供其中形成有深硅沟槽的衬底，在衬底上并在深硅沟槽内形成一层水，并将衬底暴露于氟化氢蒸气和臭氧 加油站。

公开(公告)号：US20130270512A1

公开(公告)日：2013-10-17

申请号：US13976411

申请日：2011-12-19

申请人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

发明人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US08088665B2

公开(公告)日：2012-01-03

申请号：US12228386

申请日：2008-08-11

申请人： Willy Rachmady ,  Jason W. Klaus ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack Kavalieros ,  Sean King

发明人： Willy Rachmady ,  Jason W. Klaus ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack Kavalieros ,  Sean King

IPC分类号： H01L21/336

CPC分类号： H01L29/41775 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/41783

摘要： Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.

摘要翻译： 本发明的实施例描述了在半导体器件上制造低电阻接触层的方法。 半导体器件包括具有源区和漏区的衬底。 将基板交替地暴露于第一前体和第二前体，以将非晶半导体层选择性地沉积到源极和漏极区域中的每一个上。 然后在每个源极和漏极区域上的非晶半导体层上沉积金属层。 然后在衬底上进行退火处理，以允许金属层与非晶半导体层反应，以在源极和漏极区域中的每一个上形成低电阻接触层。 根据所使用的前体的类型，源极和漏极区域中的每一个上的低电阻接触层可以形成为硅化物层或锗化物层。

公开(公告)号：US07833887B2

公开(公告)日：2010-11-16

申请号：US12145020

申请日：2008-06-24

申请人： Willy Rachmady ,  Jack Kavalieros

发明人： Willy Rachmady ,  Jack Kavalieros

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.

摘要翻译： 形成用于非平面晶体管的缺口基隔离物轮廓的方法包括提供在衬底上具有通道区域的半导体鳍片，并且形成与沟道区域的侧壁相邻并且在沟道区域的顶表面上的栅电极， 栅电极在顶表面上具有硬掩模。 使用增强的化学气相沉积（PE-CVD）工艺在栅极和散热片上沉积间隔层。 将多蚀刻工艺应用于间隔层，以在栅电极的横向相对侧上形成一对凹口，其中每个凹口位于翅片的侧壁和鳍的顶表面附近。

公开(公告)号：US20100163927A1

公开(公告)日：2010-07-01

申请号：US12319097

申请日：2008-12-30

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US07968457B2

公开(公告)日：2011-06-28

申请号：US12229881

申请日：2008-08-26

申请人： Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/44 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76867 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of an apparatus and methods for forming enhanced contacts using sandwiched metal structures are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述使用夹层金属结构形成增强触点的装置和方法的实施例。 可以描述和要求保护其他实施例。