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公开(公告)号:US09691979B2
公开(公告)日:2017-06-27
申请号:US14476748
申请日:2014-09-04
发明人: Shuo-Che Chang , Chia-Hua Ho
IPC分类号: H01L45/00
CPC分类号: H01L45/146 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1608
摘要: A resistive random access memory includes a first electrode layer, a second electrode layer, and a stacked structure disposed between the first electrode layer and the second electrode layer. The stacked structure includes a conductive layer and a resistance variable layer. The material of the conductive layer includes HfOx, the material of the resistance variable layer includes HfOy, and x
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公开(公告)号:US20190221260A1
公开(公告)日:2019-07-18
申请号:US16181372
申请日:2018-11-06
发明人: Ping-Kun Wang , Shao-Ching Liao , Yu-Ting Chen , Ming-Che Lin , Chien-Min Wu , Chia-Hua Ho
IPC分类号: G11C13/00
CPC分类号: G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C2013/0045
摘要: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
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公开(公告)号:US09166160B1
公开(公告)日:2015-10-20
申请号:US14481925
申请日:2014-09-10
发明人: Chia-Hua Ho , Shuo-Che Chang , Hsiu-Han Liao , Po-Yen Hsu , Meng-Hung Lin , Bo-Lun Wu , Ting-Ying Shen
CPC分类号: H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.
摘要翻译: 本发明提供一种电阻随机存取存储器,包括第一电极层,第二电极层和设置在第一电极层和第二电极层之间的可变电阻层,其中第二电极层包括第一子层,第二子层和 设置在第一子层和第二子层之间的导电金属氮氧化物层。
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公开(公告)号:US10658036B2
公开(公告)日:2020-05-19
申请号:US16045749
申请日:2018-07-26
发明人: Shao-Ching Liao , Ping-Kun Wang , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
摘要: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.
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公开(公告)号:US20170125673A1
公开(公告)日:2017-05-04
申请号:US15064603
申请日:2016-03-09
发明人: Po-Yen Hsu , Ting-Ying Shen , Chia-Hua Ho , Chih-Cheng Fu , Frederick Chen
IPC分类号: H01L45/00
CPC分类号: H01L45/146 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/1253 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.
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公开(公告)号:US20170018709A1
公开(公告)日:2017-01-19
申请号:US14918567
申请日:2015-10-21
发明人: Bo-Lun Wu , Chia-Hua Ho , Ting-Ying Shen , Meng-Hung Lin
CPC分类号: H01L25/18 , H01L27/0248 , H01L27/101 , H01L27/1052 , H01L27/2418 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1675
摘要: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.
摘要翻译: 本发明提供了一种存储器件及其制造方法。 存储器件包括衬底,电容器,保护器件,第一金属互连和第二金属互连。 电容器位于第一区域的基板上。 保护装置位于第二区域的基板中。 电容器包括多个底部电极,顶部电极和电容器电介质层。 顶部电极具有第一部分和第二部分,其中第二部分延伸到第二区域。 电容器介电层位于底部电极和顶部电极之间。 第一金属互连位于电容器和基板之间。 第二金属互连位于顶部电极的第二部分和保护装置之间。 顶部电极通过第二金属互连电连接到保护装置。
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公开(公告)号:US20150287915A1
公开(公告)日:2015-10-08
申请号:US14476748
申请日:2014-09-04
发明人: Shuo-Che Chang , Chia-Hua Ho
IPC分类号: H01L45/00
CPC分类号: H01L45/146 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1608
摘要: A resistive random access memory includes a first electrode layer, a second electrode layer, and a stacked structure disposed between the first electrode layer and the second electrode layer. The stacked structure includes a conductive layer and a resistance variable layer. The material of the conductive layer includes HfOx, the material of the resistance variable layer includes HfOy, and x
摘要翻译: 电阻式随机存取存储器包括第一电极层,第二电极层和布置在第一电极层和第二电极层之间的堆叠结构。 层叠结构包括导电层和电阻变化层。 导电层的材料包括HfO x,电阻变化层的材料包括HfOy和x
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公开(公告)号:US20150287914A1
公开(公告)日:2015-10-08
申请号:US14481925
申请日:2014-09-10
发明人: Chia-Hua Ho , Shuo-Che Chang , Hsiu-Han Liao , Po-Yen Hsu , Meng-Hung Lin , Bo-Lun Wu , Ting-Ying Shen
IPC分类号: H01L45/00
CPC分类号: H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.
摘要翻译: 本发明提供一种电阻随机存取存储器,包括第一电极层,第二电极层和设置在第一电极层和第二电极层之间的可变电阻层,其中第二电极层包括第一子层,第二子层和 设置在第一子层和第二子层之间的导电金属氮氧化物层。
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公开(公告)号:US20190035459A1
公开(公告)日:2019-01-31
申请号:US16045749
申请日:2018-07-26
发明人: Shao-Ching Liao , Ping-Kun Wang , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
摘要: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.
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公开(公告)号:US20190006007A1
公开(公告)日:2019-01-03
申请号:US15729676
申请日:2017-10-11
发明人: Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
IPC分类号: G11C13/00
摘要: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.
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