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公开(公告)号：US11601267B2
公开(公告)日：2023-03-07
申请号：US16361796
申请日：2019-03-22
Applicant: Winbond Electronics Corp.
Inventor： Meng-Hung Lin , Chia Hua Ho , Bo-Lun Wu
Abstract: A key generator including a first access circuit, a first calculating circuit and a first certification circuit is provided. The first access circuit writes first predetermined data to a first resistive memory cell during a write period and reads a first current passing through the first resistive memory cell after a randomization process. The first calculating circuit calculates the first current to generate a first calculation result. The first certification circuit generates a first password according to the first calculation result.
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公开(公告)号：US09166160B1
公开(公告)日：2015-10-20
申请号：US14481925
申请日：2014-09-10
Applicant: Winbond Electronics Corp.
Inventor： Chia-Hua Ho , Shuo-Che Chang , Hsiu-Han Liao , Po-Yen Hsu , Meng-Hung Lin , Bo-Lun Wu , Ting-Ying Shen
CPC classification number: H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
Abstract: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.
Abstract translation: 本发明提供一种电阻随机存取存储器，包括第一电极层，第二电极层和设置在第一电极层和第二电极层之间的可变电阻层，其中第二电极层包括第一子层，第二子层和 设置在第一子层和第二子层之间的导电金属氮氧化物层。
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公开(公告)号：US11289157B1
公开(公告)日：2022-03-29
申请号：US17012077
申请日：2020-09-04
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Kuang-Chih Hsieh , Chien-Min Wu , Meng-Hung Lin
Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.
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公开(公告)号：US20160372196A1
公开(公告)日：2016-12-22
申请号：US15088138
申请日：2016-04-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
Abstract: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.
Abstract translation: 提供了一种用于电阻式存储装置的写入方法。 在该方法中，接收逻辑数据，并且选择对应的选择存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供小于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。 当逻辑数据处于第二逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供大于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。
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公开(公告)号：US09508435B1
公开(公告)日：2016-11-29
申请号：US15088138
申请日：2016-04-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin
CPC classification number: G11C13/0097 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
Abstract: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.
Abstract translation: 提供了一种用于电阻式存储装置的写入方法。 在该方法中，接收逻辑数据，并且选择对应的选择存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供小于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。 当逻辑数据处于第二逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供大于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。
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Patent Agency Ranking
公开(公告)号：US09349451B1
公开(公告)日：2016-05-24
申请号：US14729065
申请日：2015-06-03
Applicant: Winbond Electronics Corp.
Inventor： Meng-Hung Lin , Bo-Lun Wu , Ting-Ying Shen
CPC classification number: G11C13/0097 , G11C13/0033 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0092
Abstract: A resistive memory and a repairing method of the resistive memory are provided. Steps of the repairing method includes: operating a plurality of set-reset cycles on the resistive memory; detecting whether the resistive memory encounters an over-set issue after the set-reset cycles are operated; if the resistive memory encounters the over-set issue, executing an enhanced reset programming on the resistive memory. Here, the enhanced reset programming is executed by applying an enhanced reset voltage on the resistive memory during an enhanced reset time period. A product of the enhanced reset voltage and the enhanced reset time period is larger than a product of a reset voltage and a reset time period.
Abstract translation: 提供了电阻性存储器和电阻性存储器的修复方法。 修复方法的步骤包括：在电阻性存储器上操作多个设置复位周期; 检测在设置复位周期被操作之后电阻性存储器是否遇到过度的问题; 如果电阻性存储器遇到过载问题，则在电阻性存储器上执行增强的复位编程。 这里，通过在增强的复位时间段期间在电阻存储器上施加增强的复位电压来执行增强的复位编程。 增强复位电压和增强复位时间段的乘积大于复位电压和复位时间周期的乘积。
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公开(公告)号：US20180233665A1
公开(公告)日：2018-08-16
申请号：US15949078
申请日：2018-04-10
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Po-Yen Hsu , Yi-Hsiu Chen , Ting-Ying Shen , Bo-Lun Wu , Meng-Hung Lin , Chia-Hua Ho , Ming-Che Lin
CPC classification number: H01L45/146 , H01L27/2463 , H01L45/08 , H01L45/122 , H01L45/1253 , H01L45/1266 , H01L45/1616
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
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公开(公告)号：US09972779B2
公开(公告)日：2018-05-15
申请号：US14967386
申请日：2015-12-14
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Po-Yen Hsu , Yi-Hsiu Chen , Ting-Ying Shen , Bo-Lun Wu , Meng-Hung Lin
CPC classification number: H01L45/1266 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/146
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.
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公开(公告)号：US09666570B2
公开(公告)日：2017-05-30
申请号：US14918567
申请日：2015-10-21
Applicant: Winbond Electronics Corp.
Inventor： Bo-Lun Wu , Chia-Hua Ho , Ting-Ying Shen , Meng-Hung Lin
IPC: H01L25/18 , H01L27/02 , H01L27/105 , H01L45/00 , H01L27/24
CPC classification number: H01L25/18 , H01L27/0248 , H01L27/101 , H01L27/1052 , H01L27/2418 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1675
Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.
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公开(公告)号：US09412445B1
公开(公告)日：2016-08-09
申请号：US14824081
申请日：2015-08-12
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin , Ping-Kun Wang
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C29/04 , G11C29/50 , G11C2013/0057
Abstract: A resistive memory apparatus and a reading method thereof are provided. In this method, two reading pulses are applied to a resistive memory cell, such that a first reading resistance and a second reading resistance of the resistive memory cell at different temperatures are sequentially obtained. Next, a resistive state of the second reading resistance is determined according to the reading resistances and the temperatures corresponding to the reading resistances. Thereafter, a logic level of storage data of the resistive memory cell is determined according to the resistive state of the second reading resistance.
Abstract translation: 提供了一种电阻式存储装置及其读取方法。 在该方法中，将两个读取脉冲施加到电阻性存储单元，使得在不同温度下顺次获得电阻式存储单元的第一读取电阻和第二读取电阻。 接下来，根据读取电阻和对应于读取电阻的温度来确定第二读取电阻的电阻状态。 此后，根据第二读取电阻的电阻状态来确定电阻性存储单元的存储数据的逻辑电平。
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