Key generator with resistive memory and method thereof

    公开(公告)号:US11601267B2

    公开(公告)日:2023-03-07

    申请号:US16361796

    申请日:2019-03-22

    IPC分类号: H04L9/08 G11C13/00

    摘要: A key generator including a first access circuit, a first calculating circuit and a first certification circuit is provided. The first access circuit writes first predetermined data to a first resistive memory cell during a write period and reads a first current passing through the first resistive memory cell after a randomization process. The first calculating circuit calculates the first current to generate a first calculation result. The first certification circuit generates a first password according to the first calculation result.

    Memory device
    3.
    发明授权

    公开(公告)号:US11289157B1

    公开(公告)日:2022-03-29

    申请号:US17012077

    申请日:2020-09-04

    IPC分类号: G11C13/00 H01L45/00

    摘要: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

    WRITING METHOD FOR RESISTIVE MEMORY APPARATUS
    4.
    发明申请
    WRITING METHOD FOR RESISTIVE MEMORY APPARATUS 有权
    电阻记忆装置的写入方法

    公开(公告)号:US20160372196A1

    公开(公告)日:2016-12-22

    申请号:US15088138

    申请日:2016-04-01

    IPC分类号: G11C13/00

    摘要: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.

    摘要翻译: 提供了一种用于电阻式存储装置的写入方法。 在该方法中,接收逻辑数据,并且选择对应的选择存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平时,将RESET脉冲提供给选择存储单元,然后在写入期间向选择存储单元提供小于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。 当逻辑数据处于第二逻辑电平时,将RESET脉冲提供给选择存储单元,然后在写入期间向选择存储单元提供大于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。

    Writing method for resistive memory apparatus
    5.
    发明授权
    Writing method for resistive memory apparatus 有权
    电阻式存储装置的写入方法

    公开(公告)号:US09508435B1

    公开(公告)日:2016-11-29

    申请号:US15088138

    申请日:2016-04-01

    IPC分类号: G11C11/00 G11C13/00

    摘要: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.

    摘要翻译: 提供了一种用于电阻式存储装置的写入方法。 在该方法中,接收逻辑数据,并且选择对应的选择存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平时,将RESET脉冲提供给选择存储单元,然后在写入期间向选择存储单元提供小于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。 当逻辑数据处于第二逻辑电平时,将RESET脉冲提供给选择存储单元,然后在写入期间向选择存储单元提供大于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。

    Resistive memory and repairing method thereof
    6.
    发明授权
    Resistive memory and repairing method thereof 有权
    电阻记忆及其修复方法

    公开(公告)号:US09349451B1

    公开(公告)日:2016-05-24

    申请号:US14729065

    申请日:2015-06-03

    IPC分类号: G11C11/00 G11C5/14 G11C13/00

    摘要: A resistive memory and a repairing method of the resistive memory are provided. Steps of the repairing method includes: operating a plurality of set-reset cycles on the resistive memory; detecting whether the resistive memory encounters an over-set issue after the set-reset cycles are operated; if the resistive memory encounters the over-set issue, executing an enhanced reset programming on the resistive memory. Here, the enhanced reset programming is executed by applying an enhanced reset voltage on the resistive memory during an enhanced reset time period. A product of the enhanced reset voltage and the enhanced reset time period is larger than a product of a reset voltage and a reset time period.

    摘要翻译: 提供了电阻性存储器和电阻性存储器的修复方法。 修复方法的步骤包括:在电阻性存储器上操作多个设置复位周期; 检测在设置复位周期被操作之后电阻性存储器是否遇到过度的问题; 如果电阻性存储器遇到过载问题,则在电阻性存储器上执行增强的复位编程。 这里,通过在增强的复位时间段期间在电阻存储器上施加增强的复位电压来执行增强的复位编程。 增强复位电压和增强复位时间段的乘积大于复位电压和复位时间周期的乘积。

    Resistive memory apparatus and reading method thereof
    10.
    发明授权
    Resistive memory apparatus and reading method thereof 有权
    电阻式存储装置及其读取方法

    公开(公告)号:US09412445B1

    公开(公告)日:2016-08-09

    申请号:US14824081

    申请日:2015-08-12

    摘要: A resistive memory apparatus and a reading method thereof are provided. In this method, two reading pulses are applied to a resistive memory cell, such that a first reading resistance and a second reading resistance of the resistive memory cell at different temperatures are sequentially obtained. Next, a resistive state of the second reading resistance is determined according to the reading resistances and the temperatures corresponding to the reading resistances. Thereafter, a logic level of storage data of the resistive memory cell is determined according to the resistive state of the second reading resistance.

    摘要翻译: 提供了一种电阻式存储装置及其读取方法。 在该方法中,将两个读取脉冲施加到电阻性存储单元,使得在不同温度下顺次获得电阻式存储单元的第一读取电阻和第二读取电阻。 接下来,根据读取电阻和对应于读取电阻的温度来确定第二读取电阻的电阻状态。 此后,根据第二读取电阻的电阻状态来确定电阻性存储单元的存储数据的逻辑电平。