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    NAND FLASH MEMORY
    2.
    发明申请
    NAND FLASH MEMORY 审中-公开

    公开(公告)号：US20170110196A1

    公开(公告)日：2017-04-20

    申请号：US15391969

    申请日：2016-12-28

    Applicant: Winbond Electronics Corp.

    Inventor： Robin John JIGOUR ,  Hui CHEN ,  Oron Michael

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/20 ,  G11C16/3404 ,  G11C29/04 ,  G11C29/52 ,  G11C2029/0411

    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

    Circuit for recovering from power loss and electronic device using the same circuit and method thereof
    5.
    发明授权
    Circuit for recovering from power loss and electronic device using the same circuit and method thereof 有权

    公开(公告)号：US10305470B1

    公开(公告)日：2019-05-28

    申请号：US16030778

    申请日：2018-07-09

    Applicant: Winbond Electronics Corp.

    Inventor： Oron Michael ,  Dae Hyun Kim

    IPC: H03K17/22 ,  H03L7/00 ,  H03K19/20

    Abstract: In an aspect, the disclosure is directed to a circuit which includes not limited to a memory circuit which includes a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logical comparator circuit which is connected to the memory circuit and includes a first logical comparator which compares the first memory output voltage with a first power supply voltage to generate a first logical comparator output voltage and a second logical comparator which compares the second memory output voltage with a second power supply voltage to generate a second logical comparator output voltage; and a logical circuit which is electronically connected to the logical comparator circuit and receives a first logical comparator output voltage and a second logical comparator output voltage to perform a first logical operation which is used at least in part to generate a power on reset voltage.

    Data transmission apparatus for memory and data transmission method thereof
    7.
    发明授权
    Data transmission apparatus for memory and data transmission method thereof 有权

    公开(公告)号：US10170166B1

    公开(公告)日：2019-01-01

    申请号：US15698657

    申请日：2017-09-08

    Applicant: Winbond Electronics Corp.

    Inventor： Oron Michael ,  Poongyeub Lee

    IPC: G11C7/10 ,  G11C7/06 ,  G11C7/22

    Abstract: The data transmission apparatus includes a prior stage shift register circuit and a plurality of rear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.

    Non-volatile semiconductor memory data reading method thereof
    8.
    发明授权
    Non-volatile semiconductor memory data reading method thereof 有权
    非易失性半导体存储器数据读取方法

    公开(公告)号：US09218888B2

    公开(公告)日：2015-12-22

    申请号：US14039341

    申请日：2013-09-27

    Applicant: Winbond Electronics Corp.

    Inventor： Kazuki Yamauchi ,  Katsutoshi Suito ,  Oron Michael ,  Jongjun Kim ,  Youn-Cherl Shin

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C7/06

    CPC classification number: G11C16/26 ,  G11C7/06 ,  G11C16/0483 ,  G11C16/10

    Abstract: A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.

    Abstract translation: 非挥发性半导体存储器包括存储器阵列，根据地址选择页面的选择设备，数据存储设备，存储页面数据以及输出存储的数据的输出设备。 数据存储装置包括从存储器阵列的选定页面接收数据的第一数据存储装置，从第一数据存储装置接收数据的第二数据存储装置，以及配置在第一和第二数据存储装置之间的数据发送装置 。 当第二数据存储装置的第一部分中的数据被输出时，数据传输装置将第一数据存储装置的第二部分的数据发送到第二数据存储装置，并且在第一数据存储装置的第一部分中发送数据 在第二数据存储装置的第二部分中的数据被输出时，发送到第二数据存储装置。

    DATA PROCESSIGN SYSTEM AND METHOD FOR READING INSRUCTION DATA OF INSTRUCTION FROM MEMORY
    9.
    发明申请
    DATA PROCESSIGN SYSTEM AND METHOD FOR READING INSRUCTION DATA OF INSTRUCTION FROM MEMORY 有权

    公开(公告)号：US20220179562A1

    公开(公告)日：2022-06-09

    申请号：US17111527

    申请日：2020-12-04

    Applicant: Winbond Electronics Corp.

    Inventor： Oron Michael ,  Katsutoshi Suito

    IPC: G06F3/06

    Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

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