-
公开(公告)号：US20210035647A1
公开(公告)日：2021-02-04
申请号：US16931406
申请日：2020-07-16
发明人： Makoto Senoo , Katsutoshi Suito , Tsutomu Taniguchi , Sho Okabe
摘要： A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.
-
公开(公告)号：US20220179562A1
公开(公告)日：2022-06-09
申请号：US17111527
申请日：2020-12-04
发明人： Oron Michael , Katsutoshi Suito
IPC分类号： G06F3/06
摘要： In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.
-
公开(公告)号：US09564236B2
公开(公告)日：2017-02-07
申请号：US14876828
申请日：2015-10-07
发明人： Katsutoshi Suito
CPC分类号： G11C16/26 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/24 , G11C16/3445
摘要： The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a ΔV supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process.
摘要翻译： 本公开提供了NAND闪存及其读取方法，其可以在不使用负电压产生电路的情况下读取存储器单元的负阈值。 所公开的NAND闪存包括读出放大器，位线选择电路和具有多个NAND串单元的阵列。 所公开的NAND闪速存储器包括一个ΔV提供部分元件，其在预定的时间内向源极线施加正电压，形成有选定存储单元的P阱以及与选定位线相邻的未选位线 在所选位线被预充电之后和在读取过程期间。
-
公开(公告)号：US20160163395A1
公开(公告)日：2016-06-09
申请号：US14876828
申请日：2015-10-07
发明人： Katsutoshi Suito
CPC分类号： G11C16/26 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/24 , G11C16/3445
摘要： The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a ΔV supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process.
摘要翻译： 本公开提供了NAND闪存及其读取方法，其可以在不使用负电压产生电路的情况下读取存储器单元的负阈值。 所公开的NAND闪存包括读出放大器，位线选择电路和具有多个NAND串单元的阵列。 公开的NAND快闪存储器包括一个供电部分元件，它向源极线施加一个正电压，在一个选定的存储单元中形成一个P阱以及一个与选定的位线相邻的一个未被选中的位线 在所选位线被预充电之后和在读取过程期间的预定时间段。
-
公开(公告)号：US20220413748A1
公开(公告)日：2022-12-29
申请号：US17851041
申请日：2022-06-28
发明人： Makoto Senoo , Katsutoshi Suito
IPC分类号： G06F3/06
摘要： A semiconductor memory device and an operation method capable of suppressing malfunctions and the like and performing safe operations are provided. A flash memory of the disclosure includes a controller which controls an operation based on a code read from a ROM. The operation method of the disclosure includes detecting whether the code read from the ROM has an error by a CRC processing unit; determining whether to transition to a safe mode when the code having the error is detected; and detecting and correcting the error of the code by an ECC processing unit after transitioning to the safe mode.
-
公开(公告)号：US20180090202A1
公开(公告)日：2018-03-29
申请号：US15614631
申请日：2017-06-06
IPC分类号： G11C11/56 , G11C7/10 , G11C11/408 , G11C11/4074 , H03K19/08
摘要： A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory 100 of the invention includes a memory cell array 110; a page reading element, which selects a page of the memory cell array 110 and reads out data of the selected page to a page buffer/sense circuit 180; a page information storage element 160, which stores page information related to a range of a continuous reading; and a control element 150, which controls the continuous reading of the page. The control element 150 determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.
-
公开(公告)号：US20170092368A1
公开(公告)日：2017-03-30
申请号：US15277992
申请日：2016-09-27
发明人： Katsutoshi Suito , Riichiro Shirota
IPC分类号： G11C16/14 , G11C16/04 , H01L27/115 , G11C16/34
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C16/3472 , G11C16/3477 , H01L27/11524
摘要： An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).
-
公开(公告)号：US09218888B2
公开(公告)日：2015-12-22
申请号：US14039341
申请日：2013-09-27
CPC分类号： G11C16/26 , G11C7/06 , G11C16/0483 , G11C16/10
摘要： A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.
摘要翻译： 非挥发性半导体存储器包括存储器阵列，根据地址选择页面的选择设备，数据存储设备，存储页面数据以及输出存储的数据的输出设备。 数据存储装置包括从存储器阵列的选定页面接收数据的第一数据存储装置，从第一数据存储装置接收数据的第二数据存储装置，以及配置在第一和第二数据存储装置之间的数据发送装置 。 当第二数据存储装置的第一部分中的数据被输出时，数据传输装置将第一数据存储装置的第二部分的数据发送到第二数据存储装置，并且在第一数据存储装置的第一部分中发送数据 在第二数据存储装置的第二部分中的数据被输出时，发送到第二数据存储装置。
-
公开(公告)号：US11507282B2
公开(公告)日：2022-11-22
申请号：US17111527
申请日：2020-12-04
发明人： Oron Michael , Katsutoshi Suito
摘要： In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.
-
公开(公告)号：US11315640B2
公开(公告)日：2022-04-26
申请号：US16931383
申请日：2020-07-16
发明人： Makoto Senoo , Katsutoshi Suito , Tsutomu Taniguchi , Sho Okabe
IPC分类号： G11C7/00 , G11C16/26 , G06F3/06 , G06F12/0844 , G11C7/10
摘要： A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.015 秒)