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公开(公告)号：US10957415B2
公开(公告)日：2021-03-23
申请号：US15599487
申请日：2017-05-19
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi , Katsutoshi Suito
Abstract: An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.
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公开(公告)号：US20180053568A1
公开(公告)日：2018-02-22
申请号：US15599487
申请日：2017-05-19
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi , Katsutoshi Suito
CPC classification number: G11C29/52 , G06F12/0246 , G06F2212/1032 , G06F2212/7203 , G11C7/20 , G11C16/0483 , G11C16/26 , G11C16/3404 , G11C29/04 , G11C2029/0411
Abstract: An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.
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公开(公告)号：US20160062827A1
公开(公告)日：2016-03-03
申请号：US14470948
申请日：2014-08-28
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi
CPC classification number: G11C29/52 , G06F3/0679 , G06F3/0688 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F11/1052 , G06F11/1068 , G06F2212/2022 , G06F2212/214 , G06F2212/222 , G06F2212/403 , G11C11/5628 , G11C16/10 , G11C16/3459 , G11C29/42 , G11C29/44 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor memory device is provided to keep data reliability while decreasing programming time. A NAND flash memory loads programming data from an external input/output terminal to a page buffer/sense circuit. A detecting circuit for monitoring the programming data detects whether the programming data is a specific bit string. If it is detected that the programming data is not a specific bit string, a transferring/writing circuit transfers the programming data kept by the page buffer/sense circuit to an error checking correction (ECC) circuit, and an ECC code generated by an ECC operation is written to the page buffer/sense circuit. If it is detected that the programming data is a specific bit string, transfer of the programming data kept by the page buffer/sense circuit is forbidden and a known ECC code corresponding to the specific bit string is written to the page buffer/sense circuit.
Abstract translation: 提供半导体存储器件以在减少编程时间的同时保持数据可靠性。 NAND闪存将编程数据从外部输入/输出端子加载到页面缓冲器/读出电路。 用于监视编程数据的检测电路检测编程数据是否是特定位串。 如果检测到编程数据不是特定位串，则传送/写入电路将由页面缓冲器/检测电路保存的编程数据传送到错误校验校正（ECC）电路，并且由ECC产生的ECC代码 操作被写入页面缓冲器/检测电路。 如果检测到编程数据是特定位串，则禁止由页缓冲器/检测电路保存的编程数据的传送，并将与特定位串相对应的已知ECC代码写入页缓冲器/检测电路。
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公开(公告)号：US10510421B2
公开(公告)日：2019-12-17
申请号：US16192775
申请日：2018-11-15
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi , Makoto Senoo , Hiroki Murakami
Abstract: A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.
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公开(公告)号：US10068659B2
公开(公告)日：2018-09-04
申请号：US14642391
申请日：2015-03-09
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi
Abstract: The invention provides a semiconductor memory device capable of maintaining data reliability and shortening programming time. A flash memory of the invention includes a memory array 100, a page buffer/sensor circuit 160, an input/output buffer 110 connected to an external input/output terminal, and an ECC circuit 120 for checking and correcting data errors. In a programming operation, the input/output buffer 110 loads programming data into the page buffer/sensor circuit 160 and the ECC circuit 120 in parallel. The ECC circuit 120 writes parity bits generated from ECC calculation into a spare domain of the page buffer/sensor circuit 160. After the ECC procedure, the data held by the page buffer/sensor circuit 160 are programmed to a selected page.
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Patent Agency Ranking
公开(公告)号：US20170221567A1
公开(公告)日：2017-08-03
申请号：US15182593
申请日：2016-06-15
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi , Naoaki Sudo
CPC classification number: G11C16/10 , G06F11/1068 , G11C16/30 , G11C16/3459 , G11C29/52 , G11C2211/5621
Abstract: A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspected qualification is connected with a plurality of page buffer/sensing circuits 170 via wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuit 170 includes a transistor Q2 in which a reference current Iref flows through a transistor Q1 when the programming verification is unqualified. The determination circuit 200 includes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.
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公开(公告)号：US10141036B2
公开(公告)日：2018-11-27
申请号：US15672310
申请日：2017-08-09
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi
IPC: G11C16/06 , G11C7/12 , G11C7/14 , G11C7/18 , G11C11/413 , G11C7/02 , G11C16/04 , G11C16/24 , G11C29/52 , G11C29/04
Abstract: The invention provides a semiconductor memory device and a reading method thereof, which are capable of suppressing a peak current when pre-charging a bit line are provided. The reading method of a flash memory of the present invention includes steps of: pre-charging a selected bit line; and reading a voltage or a current of the pre-charged selected bit line. The step of pre-charging is performed by pre-charging a sense node SNS to Vcc−Vth at a time t1, pre-charging a node TOBL to VCLAMP2 at a time t2, pre-charging the node TOBL to VCLAMP1 at a time t5, and pre-charging the sense node SNS to Vcc at a time t6.
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公开(公告)号：US20190213121A1
公开(公告)日：2019-07-11
申请号：US16180013
申请日：2018-11-05
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi
IPC: G06F12/02 , G11C16/10 , G11C5/02 , G06F13/42 , H01L25/065
CPC classification number: G06F12/0246 , G06F13/4282 , G11C5/02 , G11C16/107 , H01L25/0657 , H01L2224/32145
Abstract: A semiconductor memory device preventing inconsistent busy states between a plurality of memory chips is provided. A semiconductor memory device of the disclosure includes a master chip and at least one slave chip. The master chip and the slave chip include a status register capable of storing protection information. When a write-protect (WP) commend for locking the protection information of the status register is input, the protection information and lock information are programmed in a memory array. At this time, programming is controlled in a manner that a programming time in a selected memory chip is longer than a programming time in an unselected memory chip.
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公开(公告)号：US10026482B2
公开(公告)日：2018-07-17
申请号：US15239763
申请日：2016-08-17
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi
IPC: G11C16/14 , G06F11/10 , G11C16/26 , G11C16/34 , G11C29/44 , G11C16/10 , G11C16/16 , G11C16/04 , G11C29/52 , G11C7/20 , G11C29/42 , G11C29/04
Abstract: A semiconductor memory device, an erasing method and a programming method are provided. The semiconductor memory device includes a memory array, which includes a plurality of NAND strings; a page buffer/sensing circuit, which is connected to the NAND strings of the memory array through bit lines and outputs whether the NAND strings include failures; and a detecting circuit, which is connected to the plurality of page buffer/sensing circuits and detects a number of the failures among the NAND strings of a selected block. The block is determined to be usable when the number of the failures among the NAND strings detected by the detecting circuit is less than or equal to a fixed number, and the block is determined to be unusable as a bad block when the number of the failures exceeds the fixed number.
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公开(公告)号：US09947410B2
公开(公告)日：2018-04-17
申请号：US15182593
申请日：2016-06-15
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi , Naoaki Sudo
CPC classification number: G11C16/10 , G06F11/1068 , G11C16/30 , G11C16/3459 , G11C29/52 , G11C2211/5621
Abstract: A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspected qualification is connected with a plurality of page buffer/sensing circuits 170 via wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuit 170 includes a transistor Q2 in which a reference current Iref flows through a transistor Q1 when the programming verification is unqualified. The determination circuit 200 includes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.
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