公开(公告)号：US11315612B2

公开(公告)日：2022-04-26

申请号：US17216713

申请日：2021-03-30

Applicant: Winbond Electronics Corp.

Inventor： Sho Okabe

IPC: G11C7/12 ,  G11C7/10 ,  G11C5/14 ,  G11C16/04 ,  G11C16/32 ,  G11C7/22

Abstract: A semiconductor storing apparatus capable of suppressing a peak current in a pre-charge operation and shortening a sense time is provided. A pre-charge method of a bit line of an NAND type flash memory includes: turning on a transistor (BLPRE) and supplying a pre-charge voltage to a sense node (SNS) at time (t1); turning on a transistor (BLCLAMP) connected to the sense node (SNS) and used for generating a clamp voltage and turning on a transistor (BLCN) connected to a node (BLS) at time (t2), turning on a transistor (BLSe/BLSo) connected between the node (BLS) and a bit line (GBLe/GBLo) at time (t3), and performing the pre-charge operation on the bit line.

公开(公告)号：US20210326267A1

公开(公告)日：2021-10-21

申请号：US17223007

申请日：2021-04-06

Applicant: Winbond Electronics Corp.

Inventor： Sho Okabe ,  Makoto Senoo

IPC: G06F12/0891 ,  G06F11/10 ,  G06F12/0879 ,  G06F12/0882 ,  G06F12/02 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

Abstract: A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.

公开(公告)号：US20190333549A1

公开(公告)日：2019-10-31

申请号：US16368868

申请日：2019-03-29

Applicant: Winbond Electronics Corp.

Inventor： Sho Okabe

IPC: G11C5/14 ,  G11C16/32 ,  G11C16/26 ,  G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/04

Abstract: A semiconductor memory device for suppressing the peak current during the read operation is provided. A flash memory of the disclosure includes a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.

公开(公告)号：US11775441B2

公开(公告)日：2023-10-03

申请号：US17223007

申请日：2021-04-06

Applicant: Winbond Electronics Corp.

Inventor： Sho Okabe ,  Makoto Senoo

IPC: G11C16/08 ,  G06F12/0891 ,  G06F11/10 ,  G06F12/0879 ,  G06F12/0882 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G06F12/02

CPC classification number: G06F12/0891 ,  G06F11/1068 ,  G06F12/0246 ,  G06F12/0879 ,  G06F12/0882 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.

公开(公告)号：US11081181B2

公开(公告)日：2021-08-03

申请号：US16906406

申请日：2020-06-19

Applicant: Winbond Electronics Corp.

Inventor： Sho Okabe

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  G11C16/24 ,  G11C16/10 ,  G11C11/56

Abstract: A flash memory of the invention has a plurality of planes, a controller, a switch unit, and a driving control circuit. The controller is configured to select at least one of the planes. The switch unit is configured to electrically connect bit lines of the unselected plane to a reference voltage. The driving control circuit is configured to commonly provide a gate select signal to select transistors of the selected planes and the unselected planes after the bit lines of the unselected plane is electrically connected to the reference voltage. A flash memory that can reliably seek stability of threshold distribution of memory is provided.

公开(公告)号：US20210034304A1

公开(公告)日：2021-02-04

申请号：US16931383

申请日：2020-07-16

Applicant: Winbond Electronics Corp.

Inventor： Makoto Senoo ,  Katsutoshi Suito ,  Tsutomu Taniguchi ,  Sho Okabe

IPC: G06F3/06 ,  G06F12/0844

Abstract: A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).

公开(公告)号：US11488644B2

公开(公告)日：2022-11-01

申请号：US17320224

申请日：2021-05-14

Applicant: Winbond Electronics Corp.

Inventor： Sho Okabe ,  Makoto Senoo

IPC: G11C7/10 ,  G11C7/12

Abstract: A semiconductor device capable of performing high-speed read or high-reliability read is provided. A reading method of a NAND flash memory includes: pre-charging a sensing node through a voltage-supply node; discharging the sensing node to the voltage-supply node for a prescribed operation; recharging the sensing node by the voltage-supply node after the prescribed operation; and discharging a NAND string and sensing a memory cell.

公开(公告)号：US20210312957A1

公开(公告)日：2021-10-07

申请号：US17216713

申请日：2021-03-30

Applicant: Winbond Electronics Corp.

Inventor： Sho Okabe

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C16/04 ,  G11C16/32 ,  G11C5/14

Abstract: A semiconductor storing apparatus capable of suppressing a peak current in a pre-charge operation and shortening a sense time is provided. A pre-charge method of a bit line of an NAND type flash memory includes: turning on a transistor (BLPRE) and supplying a pre-charge voltage to a sense node (SNS) at time (t1); turning on a transistor (BLCLAMP) connected to the sense node (SNS) and used for generating a clamp voltage and turning on a transistor (BLCN) connected to a node (BLS) at time (t2), turning on a transistor (BLSe/BLSo) connected between the node (BLS) and a bit line (GBLe/GBLo) at time (t3), and performing the pre-charge operation on the bit line.

公开(公告)号：US20210035647A1

公开(公告)日：2021-02-04

申请号：US16931406

申请日：2020-07-16

Applicant: Winbond Electronics Corp.

Inventor： Makoto Senoo ,  Katsutoshi Suito ,  Tsutomu Taniguchi ,  Sho Okabe

IPC: G11C16/26 ,  G11C16/04

Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.

公开(公告)号：US11961568B2

公开(公告)日：2024-04-16

申请号：US17704006

申请日：2022-03-25

Applicant: Winbond Electronics Corp.

Inventor： Makoto Senoo ,  Sho Okabe

IPC: G11C16/00 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/30

Abstract: The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).