Abstract:
The present invention includes nuclear fertility restorer genes, proteins encoded by those genes and transgenic plants and plant cells containing those genes. More particularly, the nuclear fertility restorer genes can be used to restore fertility in cytoplasmic male-sterile plants such as Brassica napus. Preferably, the nuclear fertility restorer genes are used with the Ogura (ogu) CMS system in Brassica napus.
Abstract:
The present invention provides a combination dosing regimen for erythropoietin (EPO). More particularly, the present dosing regimen includes administration of at least a first dosing segment comprising a first exposure to EPO capable of stimulating the production of reticulocytes followed by a second exposure to EPO capable of sustaining the maturation of the reticulocytes into neocytes, and ultimately, red blood cells. Advantageously, the dosing segment may be cycled or repeated, any number of times and according to any desired time scheme, in order to provide or maintain any desired total red blood cell count and/or hemoglobin concentration. Methods of treatment employing the combination dosing regimen, as well as kits are also provided.
Abstract:
A mechanism for avoiding an initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller to move data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.
Abstract:
An apparatus and method for transferring data from a source memory (e.g. a host memory) to a peripheral interface via a bus utilizes a transmit buffer memory coupled to the peripheral interface, and a current time counter advancing at the rate at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table data structure stores entries in some or all of its locations, where each location corresponds to a point in time at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table pointer is used for pointing to successive locations in the schedule table. The schedule table pointer advances at a rate faster than the current time counter advances so that the schedule table pointer represents a point in time which is ahead of the point in time currently output by the current time counter. A data transfer is initiated from the source memory to the transmit buffer memory via the bus when a valid entry is stored at the location in the schedule table pointed to by the schedule table pointer. The data is then transferred out of the transmit buffer memory to the peripheral interface when the current time counter reaches the value representing at least the same point in time that was represented by the schedule table pointer when the data transfer was initiated. Data transfers from the transmit buffer memory are thereby synchronized in time with their corresponding entries in the schedule table.
Abstract:
An apparatus and method for transferring data from a source memory to a transmit buffer memory and then from the transmit buffer memory at a particular rate. A current time counter advances at the rate at which data is to be transmitted from the transmit buffer memory to the interface. A schedule memory stores entries, each valid entry being associated with data that is to be transmitted from the transmit buffer memory to the interface. A timestamp is associated with each valid entry in the schedule memory. Circuitry is then operative on each valid entry read from the schedule table to generate a request for a data transfer between the source memory and the transmit buffer memory; perform a data transfer from the source memory to the transmit buffer memory in response to the request; and transfer the data from the transmit buffer memory when the current time circuitry output reaches a value representing at least the same point in time that is represented by the timestamp associated with the entry for which the request was generated.
Abstract:
Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.
Abstract:
A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.
Abstract:
The present invention generally relates to a combination of the fields of tissue engineering, drug discovery and drug development. It more specifically provides new methods and materials for testing the efficacy and safety of experimental drugs, defining the metabolic pathways of experimental drugs and characterizing the properties (e.g., side effects, new uses) of existing drugs. Preferably, evaluation is carried out in three-dimensional tissue-engineered systems, wherein drug toxicity, metabolism, interaction and/or efficacy can be determined.
Abstract:
The present invention relates to systems and methods for obtaining optimized EPO dosage regimens for a desired pharmacodynamic/pharmacokinetic response. The system includes choosing one or more EPO dosage regimens, then using a PK/PD model to determine the pharmacodynamic/pharmacokinetic profile of one or more EPO dosage regimens, and finally selecting one of the EPO dosage regimens for administration to achieve the desired pharmacodynamic/pharmacodynamic response based on the EPO profile.
Abstract:
An expandable, modular, multi-mode lavatory for aircraft featuring its multi-mode use as a lavatory, shower and accommodations for handicapped persons. The invention comprises a primary structure with a volume that expands into adjacently located unused space, such as an aircraft's main entry cross-aisleway. Deployable walls and doors are used to create a partitioned environment. A false bottom shower pan cover provides structural support for wheelchairs while also being removable to reveal a modular shower pan for bathing.