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    Test circuit for testing a synchronous memory circuit
    1.
    发明授权
    Test circuit for testing a synchronous memory circuit 有权
    用于测试同步存储器电路的测试电路

    公开(公告)号：US07117404B2

    公开(公告)日：2006-10-03

    申请号：US10106414

    申请日：2002-03-26

    申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Peter Poechmüller ,  Jochen Mueller ,  Michael Schittenhelm

    发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Peter Poechmüller ,  Jochen Mueller ,  Michael Schittenhelm

    IPC分类号： G11C29/00

    CPC分类号： G11C29/48

    摘要： Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronous memory circuit to be tested is operable.

    摘要翻译： 用于测试具有倍频电路的同步存储电路的测试电路，该倍频电路将从外部测试单元接收的低频时钟信号的时钟频率乘以特定的倍频因子，该测试数据生成器基于数据产生测试数据 从外部测试单元接收的控制信号并将它们输出到数据输出驱动器第一信号延迟电路，用于将由测试数据发生器输出的测试数据延迟可调节的第一延迟时间;第二信号延迟电路，用于延迟数据， 从同步存储器电路中读出并由测试电路中的数据输入驱动器接收可调节的第二延迟时间，并具有数据比较电路，该数据比较电路将由测试数据发生器产生的测试数据与从 存储器电路，并且基于比较结果，向指示的外部测试单元输出指示符信号 s被测试的同步存储器电路是否可操作。

    System for testing fast integrated digital circuits, in particular semiconductor memory modules
    3.
    发明授权
    System for testing fast integrated digital circuits, in particular semiconductor memory modules 失效
    用于测试快速集成数字电路的系统，特别是半导体存储器模块

    公开(公告)号：US06721904B2

    公开(公告)日：2004-04-13

    申请号：US09907693

    申请日：2001-07-18

    申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

    发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

    IPC分类号： H02H305

    CPC分类号： G11C29/12015 ,  G11C29/48 ,  G11C29/56012

    摘要： The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

    摘要翻译： 本发明涉及一种用于测试快速集成数字电路，特别是半导体模块（例如SDRAM）的系统。 为了在DDR-SDRAM的测试中实现必要的按时间顺序的精度，同时大规模生产所需的测试系统的高度并行性，将额外的半导体电路模块（BOST模块）插入到信号中 标准测试设备和要测试的SDRAM之间的路径。 该附加模块被设置为乘以常规测试设备的相对较慢的时钟频率，并且根据测试信号来确定用于测试SDRAM模块的控制信号，地址和数据背景的信号序列 设备以及在测试前编程的寄存器内容，在BOST模块中。

    Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits
    7.
    发明授权
    Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits 有权
    用于产生用于测试高频同步数字电路的控制信号的电路配置

    公开(公告)号：US06839397B2

    公开(公告)日：2005-01-04

    申请号：US09907784

    申请日：2001-07-18

    申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

    发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

    IPC分类号： G11C29/14 ,  G06M3/00

    CPC分类号： G11C29/14

    摘要： A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

    摘要翻译： 描述用于产生用于测试高频同步数字电路，特别是存储器芯片的控制信号的电路配置。 以对应于要测试的数字电路的高时钟频率的时钟频率计时的p级移位寄存器连接到其并行加载输入p逻辑门，逻辑门逻辑地将静态控制字与动态n位置测试 字。 组合的逻辑值以低频加载时钟速率被加载到移位寄存器中，使得其值取决于在后者的时钟频率的每个时钟周期中加载到移位寄存器中的信息的控制信号 在移位寄存器的串行输出。

    Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested
    8.
    发明授权
    Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested 有权
    用于读取和检查从要测试的存储器模块读出的数据响应信号的时间位置的方法和装置

    公开(公告)号：US06871306B2

    公开(公告)日：2005-03-22

    申请号：US09907692

    申请日：2001-07-18

    申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

    发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

    IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C29/00

    CPC分类号： G11C29/50 ,  G11C29/56

    摘要： A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

    摘要翻译： 一种用于读取和检查从要测试的存储器模块读出的数据响应的时间位置的方法和装置，特别是在DDR操作中操作的DRAM存储器。 在测试接收机中，要测试的存储器模块的数据响应被锁存到具有被延迟的数据选通响应信号的数据锁存器中。 产生对称时钟信号作为校准信号。 校准信号用于校准相对于数据响应的延迟数据选通响应信号的时间位置。 延迟的数据选通响应信号用于锁存数据响应。 延迟时间在校准操作期间被编程到延迟器件中，并且还提供测量数据选通响应信号（DQS）和数据响应之间的精确时间关系。