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    Semiconductor Device with Drain-End Drift Diminution
    2.
    发明申请
    Semiconductor Device with Drain-End Drift Diminution 有权
    具有排水端漂移的半导体器件

    公开(公告)号：US20130292764A1

    公开(公告)日：2013-11-07

    申请号：US13465761

    申请日：2012-05-07

    申请人： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

    摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域 其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。 沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。 漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

    Dual gate LDMOS devices
    3.
    发明授权
    Dual gate LDMOS devices 有权
    双门LDMOS器件

    公开(公告)号：US07795674B2

    公开(公告)日：2010-09-14

    申请号：US12560588

    申请日：2009-09-16

    申请人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

    摘要： An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

    摘要翻译： N沟道器件的一个实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。 横向隔离壁围绕衬底的至少一部分并且与孔间隔开。 第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。 与第一个门相隔开的第二个栅极覆盖着N阱。 与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。 当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

    Dual gate LDMOS device fabrication methods
    6.
    发明授权
    Dual gate LDMOS device fabrication methods 失效
    双栅LDMOS器件制造方法

    公开(公告)号：US07608513B2

    公开(公告)日：2009-10-27

    申请号：US11626928

    申请日：2007-01-25

    申请人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

    摘要： An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

    摘要翻译： 描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。 横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。 第一栅极（G1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分覆盖两者。 与G1（56）间隔开的第二门（G2）（66）覆盖在N阱（44）上。 衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。 当身体接触（74）连接到G2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg2提供给G2（66）。 所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。

    Composite Semiconductor Device with Different Channel Widths
    7.
    发明申请
    Composite Semiconductor Device with Different Channel Widths 有权
    具有不同通道宽度的复合半导体器件

    公开(公告)号：US20160284841A1

    公开(公告)日：2016-09-29

    申请号：US14669415

    申请日：2015-03-26

    申请人： Won Gi Min ,  Pete Rodriquez ,  Hongning Yang ,  Jiang-Kai Zuo

    发明人： Won Gi Min ,  Pete Rodriquez ,  Hongning Yang ,  Jiang-Kai Zuo

    IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

    CPC分类号： H01L29/7816 ,  H01L27/0211 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835

    摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.

    摘要翻译： 一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构， 另一个。 第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。 第一多个晶体管结构的每个晶体管结构在饱和区域中具有比第二多个晶体管结构中的每个晶体管结构更低的电阻。

    DUAL GATE LDMOS DEVICES
    8.
    发明申请
    DUAL GATE LDMOS DEVICES 有权
    双门LDMOS器件

    公开(公告)号：US20100025765A1

    公开(公告)日：2010-02-04

    申请号：US12560588

    申请日：2009-09-16

    申请人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

    摘要： An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

    摘要翻译： N沟道器件的实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。 横向隔离壁围绕衬底的至少一部分并且与孔间隔开。 第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。 与第一个门相隔开的第二个栅极覆盖着N阱。 与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。 当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

    DUAL GATE LDMOS DEVICE AND METHOD
    9.
    发明申请
    DUAL GATE LDMOS DEVICE AND METHOD 失效
    双门LDMOS器件及方法

    公开(公告)号：US20080182394A1

    公开(公告)日：2008-07-31

    申请号：US11626928

    申请日：2007-01-25

    申请人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

    IPC分类号： H01L21/04

    CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

    摘要： An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

    摘要翻译： 描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。 横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。 第一栅极（G 1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分地覆盖两者。 与G 1（56）间隔开的第二栅极（G 2）（66）覆盖在N阱（44）上。 衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。 当主体接触件（74）连接到G 2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg 2提供给G 2（66）。 所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。