公开(公告)号：US20120238067A1

公开(公告)日：2012-09-20

申请号：US13422223

申请日：2012-03-16

申请人： Won-Cheol Jeong ,  Yun-Young Yeoh ,  Dong-Won Kim ,  Hong-Bae Park ,  Hag-Ju Cho

发明人： Won-Cheol Jeong ,  Yun-Young Yeoh ,  Dong-Won Kim ,  Hong-Bae Park ,  Hag-Ju Cho

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

摘要： Methods of fabricating semiconductor devices including providing a substrate having a channel region defined therein; forming an insulation layer on the substrate; forming a gate trench for forming a gate electrode having a sidewall portion, a bottom portion and an edge portion between the sidewall portion and the bottom portion on the insulation layer, the gate electrode trench overlapping the channel region; and forming a gate electrode in the gate electrode trench. Forming the gate electrode includes forming a first metal layer pattern in the gate electrode trench and forming a second metal layer pattern on the first metal layer pattern.

摘要翻译： 制造半导体器件的方法包括提供其中限定有沟道区的衬底; 在所述基板上形成绝缘层; 形成用于形成具有侧壁部分，底部和所述侧壁部分与所述绝缘层上的所述底部之间的边缘部分的栅电极的栅极沟槽，所述栅电极沟槽与所述沟道区重叠; 以及在所述栅电极沟槽中形成栅电极。 形成栅电极包括在栅电极沟槽中形成第一金属层图案，并在第一金属层图案上形成第二金属层图案。

公开(公告)号：US20070166931A1

公开(公告)日：2007-07-19

申请号：US11567971

申请日：2006-12-07

申请人： Hong-Bae Park ,  Hag-Ju Cho ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hong-Bae Park ,  Hag-Ju Cho ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28185 ,  H01L21/3105 ,  H01L29/513 ,  H01L29/517

摘要： A method of manufacturing a semiconductor device includes depositing a high-dielectric film on a semiconductor substrate and performing an oxygen plasma treatment on the high-dielectric film deposited on the semiconductor substrate. The method further includes forming an electrode on the oxygen-plasma treated high-dielectric film.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上沉积高电介质膜并对沉积在半导体衬底上的高电介质膜进行氧等离子体处理。 该方法还包括在氧等离子体处理的高电介质膜上形成电极。

公开(公告)号：US20060030097A1

公开(公告)日：2006-02-09

申请号：US11183651

申请日：2005-07-18

申请人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

发明人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

摘要翻译： 在集成电路器件中形成晶体管栅结构的方法可以包括在包括PMOS晶体管的第一区域的衬底上形成高k栅极绝缘层，以及包括NMOS晶体管的第二区域。 可以在第一和第二区域的高k栅极绝缘层上形成多晶硅栅极层。 可以在第一区域中的高k栅极绝缘层上直接形成金属硅化物栅极层，并且避免在第二区域中形成金属硅化物。 还公开了相关门结构。

公开(公告)号：US07399670B2

公开(公告)日：2008-07-15

申请号：US11183651

申请日：2005-07-18

申请人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

发明人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842

摘要： A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

摘要翻译： 在集成电路器件中形成晶体管栅结构的方法可以包括在包括PMOS晶体管的第一区域的衬底上形成高k栅极绝缘层，以及包括NMOS晶体管的第二区域。 可以在第一和第二区域的高k栅极绝缘层上形成多晶硅栅极层。 可以在第一区域中的高k栅极绝缘层上直接形成金属硅化物栅极层，并且避免在第二区域中形成金属硅化物。 还公开了相关门结构。

公开(公告)号：US20080023765A1

公开(公告)日：2008-01-31

申请号：US11756122

申请日：2007-05-31

申请人： Taek-Soo Jeon ,  In-Sang Kang ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee

发明人： Taek-Soo Jeon ,  In-Sang Kang ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee

IPC分类号： H01L27/01 ,  H01L21/00

CPC分类号： H01L29/78 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/42372 ,  H01L29/4966

摘要： Provided are semiconductor devices and methods of fabricating the semiconductor devices. Embodiments of such methods may include sequentially forming a gate insulation layer and a metal layer on a semiconductor substrate and etching the metal layer to form a metallic residue on the gate insulation layer. Such methods may also include monitoring an etch by-product to detect an etch endpoint for stopping the etching and forming a polysilicon layer on the gate insulation layer including the metallic residue.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 这些方法的实施例可以包括在半导体衬底上依次形成栅极绝缘层和金属层，并蚀刻金属层以在栅极绝缘层上形成金属残留物。 这样的方法还可以包括监测蚀刻副产物以检测用于停止蚀刻的蚀刻终点并在包括金属残留物的栅极绝缘层上形成多晶硅层。

公开(公告)号：US20060189055A1

公开(公告)日：2006-08-24

申请号：US11356399

申请日：2006-02-16

申请人： Hong-Bae Park ,  Hag-Ju Cho ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hong-Bae Park ,  Hag-Ju Cho ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/0228 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/40114 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： Methods of forming a composite layer, a gate structure and a capacitor are disclosed. In the methods, a first dielectric layer is atomic layer deposited on a substrate by using an oxidation gas and a first precursor gas that includes hafnium precursors. A second dielectric layer is then atomic layer deposited on the first dielectric layer by using a nitriding gas and a second precursor gas that includes hafnium precursors.

摘要翻译： 公开了形成复合层，栅极结构和电容器的方法。 在该方法中，第一电介质层通过使用氧化气体和包括铪前体的第一前体气体在原子层上沉积在衬底上。 然后通过使用氮化气体和包括铪前体的第二前体气体将第二电介质层原子层沉积在第一介电层上。

公开(公告)号：US08580629B2

公开(公告)日：2013-11-12

申请号：US13241871

申请日：2011-09-23

申请人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

发明人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.

摘要翻译： 制造半导体器件的方法可以包括：制备其中限定了第一和第二区域的衬底; 在衬底上形成包括第一和第二沟槽的层间绝缘膜; 沿着层间绝缘膜的上表面，第一沟槽的侧表面和底表面以及第二沟槽的侧表面和底表面形成包含Al和N的功函数控制膜; 在形成在第二区域中的功函数控制膜上形成掩模图案; 将工作功能控制材料注入到形成在第一区域中的功函数控制膜中，以控制形成在第一区域中的功函数控制膜的功函数; 去除掩模图案; 以及形成第一金属栅电极以填充所述第一沟槽并形成第二金属栅电极以填充所述第二沟槽。

公开(公告)号：US20070057333A1

公开(公告)日：2007-03-15

申请号：US11519063

申请日：2006-09-12

申请人： Hong-Bae Park ,  Yu-Gyun Shin

发明人： Hong-Bae Park ,  Yu-Gyun Shin

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/513 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/4925 ,  H01L29/517

摘要： Example embodiments relate to a metal-oxide-semiconductor (MOS) transistor and a method of manufacturing the MOS transistor. In a MOS transistor and a method of manufacturing the same, a gate insulation layer may be formed on the channel region of the substrate, and may further include metal oxide or metal silicate. A buffer layer may be formed on the gate insulation layer. The buffer layer may further include any one selected from the group including silicon nitride, aluminum nitride, undoped polysilicon and combinations thereof. A gate conductive layer may be formed on the buffer layer and may further include polysilicon. The buffer layer may retard or prevent a reaction between the gate conductive layer and the gate insulation layer. Source/drain regions may be further formed at surface portions of the substrate and doped with impurities. A channel region may also be further formed at the surface portion of the substrate between the source/drain regions.

摘要翻译： 示例性实施例涉及金属氧化物半导体（MOS）晶体管和制造MOS晶体管的方法。 在MOS晶体管及其制造方法中，可以在衬底的沟道区上形成栅极绝缘层，还可以包括金属氧化物或金属硅酸盐。 可以在栅极绝缘层上形成缓冲层。 缓冲层可以进一步包括从包括氮化硅，氮化铝，未掺杂的多晶硅及其组合的组中选择的任一种。 栅极导电层可以形成在缓冲层上，并且还可以包括多晶硅。 缓冲层可以延迟或防止栅极导电层和栅极绝缘层之间的反应。 源极/漏极区域可以进一步形成在衬底的表面部分并掺杂杂质。 还可以在源极/漏极区之间的衬底的表面部分处进一步形成沟道区。

公开(公告)号：US20160204108A1

公开(公告)日：2016-07-14

申请号：US15054571

申请日：2016-02-26

申请人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

发明人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

摘要翻译： 提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。 半导体衬底的第一和第二区域可以具有不同的导电类型。 第一和第二互连结构可以设置在半导体衬底上。 第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。 半导体器件可以设置在半导体模块中。

公开(公告)号：US20070120179A1

公开(公告)日：2007-05-31

申请号：US11505033

申请日：2006-08-16

申请人： Hong-Bae Park ,  Yu-Gyun Shin

发明人： Hong-Bae Park ,  Yu-Gyun Shin

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L29/513 ,  H01L29/66833

摘要： A SONOS type non-volatile memory device includes a substrate having source/drain regions doped with impurities and a channel region between the source/drain regions. A tunnel insulation layer including silicon oxide is formed on the channel region of the substrate. A charge-trapping insulation layer including silicon nitride is formed on the tunnel insulation layer. A blocking insulation layer is formed on the charge-trapping insulation layer. The blocking insulation layer has a laminate layered structure in which a plurality of layers, at least one of which includes a metal oxide layer, are sequentially stacked. An electrode is formed on the blocking insulation layer.

摘要翻译： SONOS型非易失性存储器件包括具有掺杂有杂质的源极/漏极区域和源极/漏极区域之间的沟道区域的衬底。 在衬底的沟道区上形成包括氧化硅的隧道绝缘层。 在隧道绝缘层上形成包括氮化硅的电荷捕获绝缘层。 在电荷俘获绝缘层上形成阻挡绝缘层。 隔离绝缘层具有层叠层叠结构，其中顺序层叠多个层，其中至少一层包括金属氧化物层。 在隔离绝缘层上形成电极。