利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.037 秒)

    Magnetic device
    1.
    发明授权
    Magnetic device 有权
    磁性装置

    公开(公告)号：US08772887B2

    公开(公告)日：2014-07-08

    申请号：US13475520

    申请日：2012-05-18

    申请人： Woo-Chang Lim ,  Jang-Eun Lee ,  Se-Chung Oh ,  Woo-Jin Kim ,  Young-Hyun Kim ,  Jeong-Heon Park

    发明人： Woo-Chang Lim ,  Jang-Eun Lee ,  Se-Chung Oh ,  Woo-Jin Kim ,  Young-Hyun Kim ,  Jeong-Heon Park

    IPC分类号： H01L29/82 ,  H01L43/00

    CPC分类号： H01L43/08

    摘要： A magnetic tunnel junction element is provided. The magnetic tunnel junction element has first magnetic layer and second magnetic layer formed adjacent, e.g., on lower and upper portions of an insulating layer, respectively and each having a perpendicular magnetic anisotropy, a magnetic field adjustment layer formed on the second magnetic layer and having a perpendicular magnetic anisotropy, and a bather layer formed between the magnetic field adjustment layer and the second magnetic layer. The second magnetic layer and the magnetic field adjustment layer are magnetically decoupled from each other.

    摘要翻译： 提供磁性隧道结元件。 磁性隧道结元件分别具有第一磁性层和第二磁性层，该第一磁性层和第二磁性层分别形成在例如绝缘层的下部和上部上并且各自具有垂直的磁各向异性，磁场调节层形成在第二磁性层上并具有 垂直磁各向异性，以及形成在磁场调整层和第二磁性层之间的沐浴层。 第二磁性层和磁场调节层彼此磁耦合。

    Slurry, chemical mechanical polishing method using the slurry, and method of forming metal wiring using the slurry
    4.
    发明申请
    Slurry, chemical mechanical polishing method using the slurry, and method of forming metal wiring using the slurry 审中-公开
    使用浆料的浆料，化学机械抛光方法，以及使用该浆料形成金属配线的方法

    公开(公告)号：US20090068839A1

    公开(公告)日：2009-03-12

    申请号：US12213423

    申请日：2008-06-19

    申请人： Sung-Jun Kim ,  Jeong-Heon Park ,  Chang-Ki Hong ,  Jae-Dong Lee

    发明人： Sung-Jun Kim ,  Jeong-Heon Park ,  Chang-Ki Hong ,  Jae-Dong Lee

    IPC分类号： H01L21/306

    CPC分类号： C09G1/02 ,  H01L21/3212

    摘要： A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.

    摘要翻译： 使用浆料的浆料，化学机械抛光（CMP）方法以及使用该浆料形成金属配线的方法。 浆料可以包括抛光剂，氧化剂和至少一种保护金属膜的缺陷抑制剂。 形成金属布线的CMP方法和方法可以使用一种或两种浆料，其中至少一种浆料包括至少一种缺陷抑制剂。

    Test patterns and methods of controlling CMP process using the same
    5.
    发明授权
    Test patterns and methods of controlling CMP process using the same 失效
    使用该方法控制CMP工艺的测试模式和方法

    公开(公告)号：US07294516B2

    公开(公告)日：2007-11-13

    申请号：US11055505

    申请日：2005-02-10

    申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L31/26 ,  H01L23/58

    CPC分类号： H01L22/32 ,  H01L22/34

    摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

    摘要翻译： 提供了一种测试图案和使用其的CMP控制方法。 测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。 测试图案包括平面区域和图案区域。 该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。 测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。 通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。

    Methods of fabricating thin ferroelectric layers and capacitors having ferroelectric dielectric layers therein
    6.
    发明申请
    Methods of fabricating thin ferroelectric layers and capacitors having ferroelectric dielectric layers therein 审中-公开
    制造其中具有铁电介质层的薄铁电层和电容器的方法

    公开(公告)号：US20060263909A1

    公开(公告)日：2006-11-23

    申请号：US11326485

    申请日：2006-01-05

    申请人： Suk-Hun Choi ,  Byoung-Jae Bae ,  Yoon-Ho Son ,  Chang-Ki Hong ,  Jeong-Heon Park

    发明人： Suk-Hun Choi ,  Byoung-Jae Bae ,  Yoon-Ho Son ,  Chang-Ki Hong ,  Jeong-Heon Park

    IPC分类号： H01L21/00 ,  H01L21/8242

    CPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

    摘要： Methods of forming ferroelectric layers include forming a ferroelectric layer on a substrate and chemically-mechanically polishing a surface of the ferroelectric layer by rotating a polishing pad on the surface at a rotation speed in a range from about 5 rpm to about 25 rpm. This polishing step includes pressing the polishing pad onto the surface of the ferroelectric layer at a pressure in a range from about 0.5 psi to about 3 psi. This polishing step may be followed by the step of exposing the polished surface to a rapid thermal anneal. This anneal can be performed in an inert atmosphere containing a gas selected from a group consisting of nitrogen, helium, argon and neon.

    摘要翻译： 形成铁电体层的方法包括在基板上形成铁电层，并以大约5rpm至大约25rpm的旋转速度旋转表面上的抛光垫，对铁电层的表面进行化学机械抛光。 该抛光步骤包括在约0.5psi至约3psi范围内的压力下将抛光垫压在铁电层的表面上。 该抛光步骤之后可以将抛光表面暴露于快速热退火的步骤。 该退火可以在含有选自氮，氦，氩和氖的气体的惰性气氛中进行。

    Test patterns and methods of controlling CMP process using the same
    8.
    发明申请
    Test patterns and methods of controlling CMP process using the same 失效

    公开(公告)号：US20050145602A1

    公开(公告)日：2005-07-07

    申请号：US11055505

    申请日：2005-02-10

    申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/66 ,  C03C25/68 ,  C23F1/00 ,  G01R31/26 ,  H01L21/4763 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/32 ,  H01L22/34

    摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

    Test patterns and methods of controlling CMP process using the same
    9.
    发明授权
    Test patterns and methods of controlling CMP process using the same 失效
    使用该方法控制CMP工艺的测试模式和方法

    公开(公告)号：US06875997B2

    公开(公告)日：2005-04-05

    申请号：US10396595

    申请日：2003-03-25

    申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/66 ,  C03C25/68 ,  C23F1/00 ,  G01R31/26 ,  H01L21/4763 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/32 ,  H01L22/34

    摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

    摘要翻译： 提供了一种测试图案和使用其的CMP控制方法。 测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。 测试图案包括平面区域和图案区域。 该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。 测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。 通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。