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    Slurry, chemical mechanical polishing method using the slurry, and method of forming metal wiring using the slurry
    2.
    发明申请
    Slurry, chemical mechanical polishing method using the slurry, and method of forming metal wiring using the slurry 审中-公开
    使用浆料的浆料，化学机械抛光方法，以及使用该浆料形成金属配线的方法

    公开(公告)号：US20090068839A1

    公开(公告)日：2009-03-12

    申请号：US12213423

    申请日：2008-06-19

    申请人： Sung-Jun Kim ,  Jeong-Heon Park ,  Chang-Ki Hong ,  Jae-Dong Lee

    发明人： Sung-Jun Kim ,  Jeong-Heon Park ,  Chang-Ki Hong ,  Jae-Dong Lee

    IPC分类号： H01L21/306

    CPC分类号： C09G1/02 ,  H01L21/3212

    摘要： A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.

    摘要翻译： 使用浆料的浆料，化学机械抛光（CMP）方法以及使用该浆料形成金属配线的方法。 浆料可以包括抛光剂，氧化剂和至少一种保护金属膜的缺陷抑制剂。 形成金属布线的CMP方法和方法可以使用一种或两种浆料，其中至少一种浆料包括至少一种缺陷抑制剂。

    Test patterns and methods of controlling CMP process using the same
    6.
    发明授权
    Test patterns and methods of controlling CMP process using the same 失效
    使用该方法控制CMP工艺的测试模式和方法

    公开(公告)号：US06875997B2

    公开(公告)日：2005-04-05

    申请号：US10396595

    申请日：2003-03-25

    申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/66 ,  C03C25/68 ,  C23F1/00 ,  G01R31/26 ,  H01L21/4763 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/32 ,  H01L22/34

    摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

    摘要翻译： 提供了一种测试图案和使用其的CMP控制方法。 测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。 测试图案包括平面区域和图案区域。 该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。 测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。 通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。

    Test patterns and methods of controlling CMP process using the same
    7.
    发明申请
    Test patterns and methods of controlling CMP process using the same 失效

    公开(公告)号：US20050145602A1

    公开(公告)日：2005-07-07

    申请号：US11055505

    申请日：2005-02-10

    申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/66 ,  C03C25/68 ,  C23F1/00 ,  G01R31/26 ,  H01L21/4763 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/32 ,  H01L22/34

    摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

    Test patterns and methods of controlling CMP process using the same
    8.
    发明授权
    Test patterns and methods of controlling CMP process using the same 失效
    使用该方法控制CMP工艺的测试模式和方法

    公开(公告)号：US07294516B2

    公开(公告)日：2007-11-13

    申请号：US11055505

    申请日：2005-02-10

    申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L31/26 ,  H01L23/58

    CPC分类号： H01L22/32 ,  H01L22/34

    摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

    摘要翻译： 提供了一种测试图案和使用其的CMP控制方法。 测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。 测试图案包括平面区域和图案区域。 该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。 测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。 通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。