公开(公告)号：US20070264820A1

公开(公告)日：2007-11-15

申请号：US11434318

申请日：2006-05-15

申请人： Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Hsia ,  Boon Seah ,  Shyam Pal

发明人： Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Hsia ,  Boon Seah ,  Shyam Pal

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76814

摘要： An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

摘要翻译： 本发明的一个实施例示出了一种形成镶嵌开口的方法，优选地不具有硬掩模悬垂或电介质层底切/空隙。 低k电介质材料可以被夹在两个硬掩模膜中以形成蚀刻互连开口的电介质膜。 第一示例性实施例包括以下。 我们在半导体结构上形成下互连和绝缘层。 我们在下互连和绝缘层上形成第一硬掩模介电层和第二硬掩模层。 我们蚀刻第一硬掩模，电介质层和第二硬掩模层中的第一互连开口。 最后，我们在第一个互连开口中形成互连。

公开(公告)号：US20050191851A1

公开(公告)日：2005-09-01

申请号：US11119274

申请日：2005-04-29

申请人： Wuping Liu ,  Beichao Zhang ,  Liang Hsia

发明人： Wuping Liu ,  Beichao Zhang ,  Liang Hsia

IPC分类号： H01L21/768 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76849 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76865 ,  H01L21/76877

摘要： A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.

摘要翻译： 提供了一种用于创建镶嵌铜互连的新方法。 提供了一种方法，由此产生的铜表面被一层屏障材料盖住。 通过阻挡材料的盖结构，所制造的铜互连的表面被屏蔽以防止诸如加工化学品的影响等外部影响。 作为阻挡材料盖的形成的结果，消除了铜氧化，铜背溅射等的常规问题。

公开(公告)号：US07323408B2

公开(公告)日：2008-01-29

申请号：US11299457

申请日：2005-12-12

申请人： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

发明人： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

摘要翻译： 提供了一种用于创建铜互连的新方法。 产生铜互连的图案，半导体材料的保护层沉积在所产生的铜互连的表面上。 保护层被图案化和蚀刻，暴露铜互连图案的表面。 暴露的铜表面是Ar溅射，之后沉积第一势垒层。 去除保护材料的图案化和蚀刻层，留在覆盖铜图案的位置使第一阻挡材料的保护层互连。 沉积了一层蚀刻停止材料形式的电介质阻挡层，之后沉积了分层的蚀刻停止材料层。 通孔和沟槽图案被蚀刻成与将要建立电接触的铜图案对齐，铜图案被第一层屏障材料保护。 沉积第二阻挡层，通孔和沟槽图案填充有铜，之后通过抛光沉积的铜层的表面去除多余的铜。

公开(公告)号：US07153766B2

公开(公告)日：2006-12-26

申请号：US10339188

申请日：2003-01-09

申请人： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

发明人： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

公开(公告)号：US20060088995A1

公开(公告)日：2006-04-27

申请号：US11299457

申请日：2005-12-12

申请人： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

发明人： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

摘要翻译： 提供了一种用于创建铜互连的新方法。 产生铜互连的图案，半导体材料的保护层沉积在所产生的铜互连的表面上。 保护层被图案化和蚀刻，暴露铜互连图案的表面。 暴露的铜表面是Ar溅射，之后沉积第一势垒层。 去除保护材料的图案化和蚀刻层，留在覆盖铜图案的位置使第一阻挡材料的保护层互连。 沉积了一层蚀刻停止材料形式的电介质阻挡层，之后沉积了分层的蚀刻停止材料层。 通孔和沟槽图案被蚀刻成与将要建立电接触的铜图案对齐，铜图案被第一层屏障材料保护。 沉积第二阻挡层，通孔和沟槽图案填充有铜，之后通过抛光沉积的铜层的表面去除多余的铜。

公开(公告)号：US07601607B2

公开(公告)日：2009-10-13

申请号：US11434318

申请日：2006-05-15

申请人： Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Choo Hsia ,  Boon Meng Seah ,  Shyam Pal

发明人： Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Choo Hsia ,  Boon Meng Seah ,  Shyam Pal

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76814

摘要： An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

摘要翻译： 本发明的一个实施例示出了一种形成镶嵌开口的方法，优选地不具有硬掩模悬垂或电介质层底切/空隙。 低k电介质材料可以被夹在两个硬掩模膜中以形成蚀刻互连开口的电介质膜。 第一示例性实施例包括以下。 我们在半导体结构上形成下互连和绝缘层。 我们在下互连和绝缘层上形成第一硬掩模介电层和第二硬掩模层。 我们蚀刻第一硬掩模，电介质层和第二硬掩模层中的第一互连开口。 最后，我们在第一个互连开口中形成互连。

公开(公告)号：US20050090097A1

公开(公告)日：2005-04-28

申请号：US10692028

申请日：2003-10-23

申请人： Beichao Zhang ,  Chun Low ,  Hong Lee ,  Sang Loong ,  Giang Guo

发明人： Beichao Zhang ,  Chun Low ,  Hong Lee ,  Sang Loong ,  Giang Guo

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

摘要翻译： 描述了一种用于提高半导体器件中的电迁移阻力的集成方法。 在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。 一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。 在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。 另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。 发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

公开(公告)号：US07045455B2

公开(公告)日：2006-05-16

申请号：US10692028

申请日：2003-10-23

申请人： Beichao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

发明人： Beichao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

摘要翻译： 描述了一种用于提高半导体器件中的电迁移阻力的集成方法。 在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。 一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。 在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。 另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。 发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

公开(公告)号：US20090315115A1

公开(公告)日：2009-12-24

申请号：US12214854

申请日：2008-06-23

申请人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

发明人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L29/7846

摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.

摘要翻译： 制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。 在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。 这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。 将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。 将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

公开(公告)号：US20070264824A1

公开(公告)日：2007-11-15

申请号：US11434343

申请日：2006-05-15

申请人： Yong Siew ,  Beichao Zhang

发明人： Yong Siew ,  Beichao Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/76895 ,  H01L21/02074 ,  H01L21/7684 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed over the first barrier layer. The second barrier layer is comprised of TaN or WN. We planarize a first conductive layer to form a first contact plug in the contact hole. We reactive ion etch ( e.g., W touch up etch) the top surfaces using a Cl and B containing etch. Because of the composition of the barrier layers and RIE etch chemistry, the barrier layers are not significantly etched selectively to the dielectric layer. In a second embodiment, a barrier film is comprised of WN.

摘要翻译： 使用接触式RIE形成阻挡层和接触塞的方法。 在第一实施例中，我们在电介质层和接触孔中的衬底之间形成第一阻挡层。 第一阻挡层由Ta构成。 在第一阻挡层上形成第二阻挡层。 第二阻挡层由TaN或WN构成。 我们平面化第一导电层以在接触孔中形成第一接触塞。 我们使用含Cl和B的蚀刻反应离子蚀刻（例如，W触摸上蚀刻）顶表面。 由于阻挡层的组成和RIE蚀刻化学，阻挡层没有被有选择地蚀刻到电介质层。 在第二实施例中，阻挡膜由WN构成。