摘要:
An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.
摘要:
A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.
摘要:
A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.
摘要:
An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.
摘要:
A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.
摘要:
A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.
摘要:
In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.
摘要:
In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.
摘要:
An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.
摘要:
In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.