公开(公告)号：US20250030500A1

公开(公告)日：2025-01-23

申请号：US18223517

申请日：2023-07-18

Applicant: XILINX, INC.

Inventor： Millind MITTAL ,  Krishnan SRINIVASAN ,  Kenneth MA

IPC: H04L1/00 ,  H04L49/9005

Abstract: Some examples described herein provide for interconnect in chiplet systems, for example system-level techniques for error correction in chip-to-chip interfaces. In an example, a method of error correction includes receiving, at a first chiplet, a data message via a set of interconnect, and transmitting a first control message that requests retransmission of the data message based on detecting an error associated with receiving the data message. The method also includes transmitting one or more instances of a second control message that indicates an idle operation at the first chiplet until the first chiplet receives a third control message that triggers an end of a retransmission mode. The method also includes transmitting a fourth control message frame indicating the end of the retransmission mode, and receiving a retransmission of the data message from the second chiplet.

公开(公告)号：US20240313781A1

公开(公告)日：2024-09-19

申请号：US18123160

申请日：2023-03-17

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sagheer AHMAD ,  Trevor J. BAUER ,  Kenneth MA ,  David P. SCHULTZ ,  John O'DWYER ,  Richard W. SWANSON ,  Bhuvanachandran K. NAIR ,  Millind MITTAL

IPC: H03K19/17736 ,  G01R31/317 ,  H03K19/0175 ,  H03K19/17796

CPC classification number: H03K19/17744 ,  G01R31/31701 ,  H03K19/017581 ,  H03K19/17796

Abstract: Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.

公开(公告)号：US20250167152A1

公开(公告)日：2025-05-22

申请号：US19032979

申请日：2025-01-21

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Kenneth MA ,  Balakrishna JAYADEV ,  Sagheer AHMAD

IPC: H01L23/00 ,  G11C5/06 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US20240014161A1

公开(公告)日：2024-01-11

申请号：US18369115

申请日：2023-09-15

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Kenneth MA ,  Balakrishna JAYADEV ,  Sagheer AHMAD

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L25/0657 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2924/1434 ,  H01L2225/0651

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).