公开(公告)号：US20160217835A1

公开(公告)日：2016-07-28

申请号：US14607978

申请日：2015-01-28

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

IPC: G11C7/10 ,  G06F12/02 ,  G06F12/08

CPC classification number: G11C7/1057 ,  G06F12/0246 ,  G06F12/0813 ,  G06F13/1694 ,  G06F2212/7203 ,  G11C7/1072

Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.

Abstract translation: 描述用于控制具有不同类型的存储器的存储器系统的操作的电路。 该电路包括具有第一类型的存储元件并且具有第一存取时间的第一存储器; 具有第二类型的存储元件并具有第二存取时间的第二存储器，其中所述第二类型的存储元件不同于所述第一类型的存储元件; 存储器控制电路，其能够访问第一存储器和第二存储器; 延迟缓冲器，其耦合到所述第二存储器，以补偿所述第一访问时间和所述第二访问时间的差异; 以及用于合并第一存储器的输出和第二存储器的延迟输出的电路，以产生有序的输出数据。 还公开了一种控制存储器系统的操作的方法。

公开(公告)号：US11934932B1

公开(公告)日：2024-03-19

申请号：US17094598

申请日：2020-11-10

Applicant: XILINX, INC.

Inventor： Giulio Gambardella ,  Nicholas Fraser ,  Ussama Zahid ,  Michaela Blott ,  Kornelis A. Vissers

IPC: G06N20/20 ,  G06F11/16 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06N20/20 ,  G06F11/16 ,  G06N3/045 ,  G06N3/08

Abstract: Examples herein propose operating redundant ML models which have been trained using a boosting technique that considers hardware faults. The embodiments herein describe performing an evaluation process where the performance of a first ML model is measured in the presence of a hardware fault. The errors introduced by the hardware fault can then be used to train a second ML model. In one embodiment, a second evaluation process is performed where the combined performance of both the first and second trained ML models is measured in the presence of a hardware fault. The resulting errors can then be used when training a third ML model. In this manner, the three trained ML models are trained to be error aware. As a result, during operation, if a hardware fault occurs, the three ML models have better performance relative to three ML models that where not trained to be error aware.

公开(公告)号：US20190080223A1

公开(公告)日：2019-03-14

申请号：US15705033

申请日：2017-09-14

Applicant: Xilinx, Inc.

Inventor： Nicholas Fraser ,  Michaela Blott

IPC: G06N3/04 ,  G06N3/08

Abstract: A neural network system includes an input layer, one or more hidden layers, and an output layer. The input layer receives a training set including a sequence of batches and provides to its following layer output activations associated with the sequence of batches respectively. A first hidden layer receives, from its preceding layer, a first input activation associated with a first batch, receive a first input gradient associated with a second batch preceding the first batch, and provide, to its following layer a first output activation associated with the first batch based on the first input activation and first input gradient. The first and second batches have a delay factor associated with at least two batches. The output layer receives, from its preceding layer, a second input activation, and provide, to its preceding layer, a first output gradient based on the second input activation and the first training set.

公开(公告)号：US10320918B1

公开(公告)日：2019-06-11

申请号：US14574283

申请日：2014-12-17

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  David A. Sidler ,  Kimon Karras ,  Raymond Carley ,  Kornelis A. Vissers

IPC: G06F15/16 ,  H04L29/08 ,  H04L12/741

Abstract: In an example, an integrated circuit (IC) includes a receive circuit, a transmit circuit, and a control circuit. The receive circuit includes a receive data path and a receive control interface, the receive data path coupled to store received transmission control protocol (TCP) data for a plurality of TCP sessions in a respective plurality of receive buffers in an external memory circuit external to the IC. The transmit circuit includes a transmit data path and a transmit control interface, the transmit data path coupled to read TCP data to be transmitted for the plurality of TCP sessions from a respective plurality of transmit buffers in the external memory circuit. The control circuit is coupled to the receive control interface and the transmit control interface, the control circuit configured to maintain data structures to maintain TCP state information for the plurality of TCP sessions.

公开(公告)号：US09519486B1

公开(公告)日：2016-12-13

申请号：US13683720

申请日：2012-11-21

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Thomas B. English ,  Kornelis A. Vissers

IPC: G06F13/00 ,  G06F9/38 ,  G06F15/78 ,  H03K19/177

CPC classification number: G06F9/3867 ,  G06F9/3897 ,  G06F15/7867 ,  G06F15/7878 ,  H03K19/17752 ,  H03K19/17756

Abstract: A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.

Abstract translation: 描述了一种在集成电路中处理数据的方法。 该方法包括建立处理块流水线，其中每个处理块具有不同的功能; 将具有数据和元数据的数据分组耦合到处理块的流水线的输入; 以及使用基于所述元数据的预定处理块来处理所述数据分组的数据。 还描述了用于处理集成电路中的数据的装置。

公开(公告)号：US20150311899A1

公开(公告)日：2015-10-29

申请号：US14260580

申请日：2014-04-24

Applicant: Xilinx, Inc.

Inventor： Kimon Karras ,  Michaela Blott ,  Kornelis A. Vissers

IPC: H03K19/177 ,  G06F17/50

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17724

Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract translation: 可编程IC包括多个可编程资源，耦合到多个可编程资源的多个可共享逻辑电路和虚拟化电路。 多个可编程资源包括可编程逻辑电路和可编程路由资源。 虚拟化电路被配置为管理在多个可编程资源中实现的多个用户设计之间的多个可共享逻辑电路的共享。 用户设计在可编程IC上彼此通信隔离。

公开(公告)号：US11615300B1

公开(公告)日：2023-03-28

申请号：US16007884

申请日：2018-06-13

Applicant: Xilinx, Inc.

Inventor： Julian Faraone ,  Michaela Blott ,  Nicholas Fraser

IPC: G06N3/08 ,  G06N3/04

Abstract: A neural network system includes an input layer, one or more hidden layers, and an output layer. A first layer circuit implements a first layer of the one or more hidden layers. The first layer includes a first weight space including one or more subgroups. A forward path circuit of the first layer circuit includes a multiply and accumulate circuit to receive an input from a layer preceding the first layer; and provide a first subgroup weighted sum using the input and a first plurality weights associated with a first subgroup. A scaling coefficient circuit provides a first scaling coefficient associated with the first subgroup, and applies the first scaling coefficient to the first subgroup weighted sum to generate a first subgroup scaled weighted sum. An activation circuit generates an activation based on the first subgroup scaled weighted sum and provide the activation to a layer following the first layer.

公开(公告)号：US10482054B1

公开(公告)日：2019-11-19

申请号：US15261626

申请日：2016-09-09

Applicant: Xilinx, Inc.

Inventor： Ling Liu ,  Michaela Blott ,  Kimon Karras ,  Thomas Janson ,  Kornelis A. Vissers

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L12/861

Abstract: The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.

公开(公告)号：US20180039886A1

公开(公告)日：2018-02-08

申请号：US15230164

申请日：2016-08-05

Applicant: Xilinx, Inc.

Inventor： Yaman Umuroglu ,  Michaela Blott

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  H03K19/17732

Abstract: In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.

公开(公告)号：US09323457B2

公开(公告)日：2016-04-26

申请号：US14100250

申请日：2013-12-09

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

IPC: G06F12/00 ,  G06F3/06 ,  G06F17/30 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/466 ,  G06F12/00 ,  G06F13/00 ,  G06F17/30221 ,  G06F17/30312 ,  G06F17/30519

Abstract: A circuit for processing data is described. The circuit comprises an input for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store; and a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion.

Abstract translation: 描述用于处理数据的电路。 电路包括用于接收实现键值存储数据事务的请求的输入; 与能够访问与键值存储相关联的多个存储器件的不同存储器类型相关联的多个存储器接口; 以及存储器管理电路，其基于数据传输标准，通过多个存储器接口来控制数据的路由。