公开(公告)号：US20180012853A1

公开(公告)日：2018-01-11

申请号：US15643012

申请日：2017-07-06

Applicant: XINTEC INC.

Inventor： Hsi-Chien LIN ,  Jyh-Wei CHEN ,  Jun-Chi HSIEH ,  Yue-Ting CHEN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  G06K9/00

CPC classification number: H01L24/02 ,  G06K9/00013 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/94 ,  H01L24/96 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14685 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/03019 ,  H01L2224/04105 ,  H01L2224/08221 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73259 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/10155 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/19

Abstract: A chip package includes a chip, an isolation layer on the bottom surface and the sidewall, a redistribution layer that is on the isolation layer and in electrical contact with a side surface of the conductive pad, and a passivation layer. The chip has a sensor, at least one conductive pad, a top surface, a bottom surface, and a sidewall. The sensor is located on the top surface. The conductive pad is located on an edge of the top surface. The redistribution layer at least partially protrudes from the conductive pad so as to be exposed. The passivation layer is located on the isolation layer and the redistribution layer, such that the redistribution layer not protruding from the conductive pad is between the passivation layer and the isolation layer, and the redistribution layer protruding from the conductive pad is located on the passivation layer.

公开(公告)号：US20170025370A1

公开(公告)日：2017-01-26

申请号：US15209723

申请日：2016-07-13

Applicant: XINTEC INC.

Inventor： Yin-Chen CHEN ,  Jan-Lian LIAO ,  Ming-Chieh HUANG ,  Jyh-Wei CHEN ,  Hsi-Chien LIN

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/06 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/29 ,  H01L24/43 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0605 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

Abstract translation: 本发明提供了一种制造芯片级感测芯片封装的方法，包括以下步骤：提供具有彼此相对的第一顶表面和第一底表面的感测装置晶片，由此感测装置晶片包括多个芯片 区域，并且每个芯片区域包括感测装置和与第一顶表面附近的感测芯片相邻的多个导电焊盘; 提供具有彼此相对的第二顶表面和第二底表面的盖晶片，并且通过在其间夹住第一粘合剂层将盖晶片的第二表面粘合到感测装置晶片的第一顶表面; 提供临时载体基板，并且通过在其间夹着第二粘合剂层将临时载体基板结合到盖晶片的第二顶表面; 形成连接到感测装置晶片的第一底表面上的每个导电焊盘的布线层; 在所述布线层上提供第一保护层; 去除所述临时载体基板和所述第二粘合剂层; 在所述第二顶表面上形成第二保护层; 去除第一保护层; 划片芯片区域以产生多个单独的芯片级感测芯片封装; 并移除第二保护层。