公开(公告)号：US10446504B2

公开(公告)日：2019-10-15

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Po-Han Lee ,  Wei-Chung Yang ,  Kuan-Jung Wu ,  Shu-Ming Chang

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L27/146

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

公开(公告)号：US10056419B2

公开(公告)日：2018-08-21

申请号：US15895575

申请日：2018-02-13

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

公开(公告)号：US09966358B2

公开(公告)日：2018-05-08

申请号：US15164660

申请日：2016-05-25

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/492 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/14618 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/16235

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

公开(公告)号：US20130127001A1

公开(公告)日：2013-05-23

申请号：US13674264

申请日：2012-11-12

Applicant: Xintec Inc.

Inventor： Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L31/0232 ,  H01L25/167 ,  H01L27/14618 ,  H01L31/02325 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor package is provided, including a silicon-containing substrate, a photo-sensor chip disposed on the silicon-containing substrate, a plurality of conductive lines electrically connected to the silicon-containing substrate and the photo-sensor chip, an encapsulating layer encapsulating the photo-sensor chip and the conductive lines, and a colloid lens disposed on the encapsulating layer. With the photo-sensor chip stacked on the silicon-containing substrate, a circuit board may have a reduced region that is occupied by the semiconductor package. A method of fabricating the semiconductor package is also provided.

Abstract translation: 提供了一种半导体封装件，包括含硅衬底，设置在含硅衬底上的光电传感器芯片，与该含硅衬底和光电传感器芯片电连接的多个导电线，封装层 光传感器芯片和导电线，以及设置在封装层上的胶体透镜。 利用光电传感器芯片堆叠在含硅衬底上，电路板可以具有被半导体封装占据的减小的区域。 还提供了制造半导体封装的方法。

公开(公告)号：US09935148B2

公开(公告)日：2018-04-03

申请号：US15181291

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

公开(公告)号：US10157875B2

公开(公告)日：2018-12-18

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L27/146 ,  H01L25/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.