公开(公告)号：US08861669B2

公开(公告)日：2014-10-14

申请号：US12571210

申请日：2009-09-30

申请人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

发明人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

IPC分类号： H03D3/24 ,  H03L7/197 ,  H04N21/43 ,  H03L7/193 ,  H04N21/41 ,  H04J3/06 ,  G09G5/00

CPC分类号： H04J3/062 ,  G09G5/008 ,  H03L7/193 ,  H03L7/1978 ,  H04N21/4122 ,  H04N21/4307

摘要： The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

摘要翻译： 本公开提供了用于在高清晰度多媒体数字内容传输系统中的信宿处恢复源流时钟数据的技术。 本公开包括基于分数N锁相环（PLL）的时钟发生器，可编程Σ-Δ调制器（SDM）和时钟数据校准器，以完全恢复原始源流时钟数据。 分数N PLL提供灵活的源流时钟恢复。 当原始时钟与再生时钟之间存在频率偏差时，时钟数据校准器控制电路调整时钟数据，防止任何流数据缓冲区溢出或下溢问题。 所公开的技术基于DisplayPort和HDMI的标准与宿设备兼容。

公开(公告)号：US07750696B2

公开(公告)日：2010-07-06

申请号：US12077929

申请日：2008-03-20

申请人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

发明人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  H03L7/0891

摘要： A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

摘要翻译： 一种校准PLL的方法，其包括强制输入到压控振荡器的控制电压作为参考电压，并且设置耦合以从压控振荡器接收输出时钟信号的校准分配器，使得校准分配器利用多个 导致输出时钟信号具有高频率的除数可以基本上避免与常规PLL校准相关的过冲和毛刺问题。

公开(公告)号：US20110075782A1

公开(公告)日：2011-03-31

申请号：US12571210

申请日：2009-09-30

申请人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

发明人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

IPC分类号： H04L7/00

CPC分类号： H04J3/062 ,  G09G5/008 ,  H03L7/193 ,  H03L7/1978 ,  H04N21/4122 ,  H04N21/4307

摘要： The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

摘要翻译： 本公开提供了用于在高清晰度多媒体数字内容传输系统中的信宿处恢复源流时钟数据的技术。 本公开包括基于分数N锁相环（PLL）的时钟发生器，可编程Σ-Δ调制器（SDM）和时钟数据校准器，以完全恢复原始源流时钟数据。 分数N PLL提供灵活的源流时钟恢复。 当原始时钟与再生时钟之间存在频率偏差时，时钟数据校准器控制电路调整时钟数据，防止任何流数据缓冲区溢出或下溢问题。 所公开的技术基于DisplayPort和HDMI的标准与宿设备兼容。

公开(公告)号：US20090237132A1

公开(公告)日：2009-09-24

申请号：US12077929

申请日：2008-03-20

申请人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

发明人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

IPC分类号： H03L7/085

CPC分类号： H03L7/18 ,  H03L7/0891

摘要： A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

摘要翻译： 一种校准PLL的方法，其包括强制输入到压控振荡器的控制电压作为参考电压，并且设置耦合以从压控振荡器接收输出时钟信号的校准分配器，使得校准分配器利用多个 导致输出时钟信号具有高频率的除数可以基本上避免与常规PLL校准相关的过冲和毛刺问题。

公开(公告)号：US07571337B1

公开(公告)日：2009-08-04

申请号：US11136056

申请日：2005-05-24

申请人： Shubing Zhai ,  Xiaoqian Zhang

发明人： Shubing Zhai ,  Xiaoqian Zhang

IPC分类号： G06F13/42

CPC分类号： H04L7/0338 ,  G11C27/02 ,  H04L7/0008

摘要： A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to shift the plurality of clock signals relative to a reference clock signal responsive to a first control signal. The data output circuit further includes a clock signal selector that selectively applies the plurality of clock signals to the data output buffers responsive to a second control signal. The adjustable multiphase clock signal generator may include, for example, a control loop, such as a phase locked loop or a delay locked loop, which selectively feeds back one of the plurality of clock signals responsive to the first control signal. The clock signal selector may include a plurality of clock signal selectors, respective ones of which receive the plurality of clock signals and selectively apply the plurality of clock signals to respective ones of the data output buffers responsive to the second control signal.

摘要翻译： 数据输出电路包括多个时钟数据输出缓冲器，每个时钟数据输出缓冲器响应于时钟信号驱动其数据输出，以及可调多相时钟信号发生器，其产生不同相位的多个时钟信号， 响应于第一控制信号的相对于参考时钟信号的多个时钟信号。 数据输出电路还包括时钟信号选择器，其响应于第二控制信号而选择性地将多个时钟信号施加到数据输出缓冲器。 可调节多相时钟信号发生器可以包括例如响应于第一控制信号选择性地反馈多个时钟信号中的一个的控制环路，例如锁相环或延迟锁定环路。 时钟信号选择器可以包括多个时钟信号选择器，其中各个时钟信号选择器接收多个时钟信号，并且响应于第二控制信号有选择地将多个时钟信号施加到数据输出缓冲器中的相应数据输出缓冲器。

公开(公告)号：US20050226243A1

公开(公告)日：2005-10-13

申请号：US10861897

申请日：2004-06-04

申请人： Shubing Zhai ,  Yefei Sun ,  Xiaoqian Zhang ,  Zhonghai Gan

发明人： Shubing Zhai ,  Yefei Sun ,  Xiaoqian Zhang ,  Zhonghai Gan

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L29/06 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L49/103 ,  H04L69/324

摘要： Data received from a bursty interface is received on a burst-by-burst basis. Once a burst is received, it is stored in a processing queue. A complete burst is received so long a processing queue can accommodate a data burst. The complete data burst is directed to an output and used to create a complete data burst on said output. The output burst is dispatched so long as a receiving port is able to accept the output burst.

摘要翻译： 从突发接口接收的数据以突发为基础接收。 一旦接收到脉冲串，它就被存储在处理队列中。 接收到完整的脉冲串，处理队列可以容纳数据脉冲串。 完整的数据脉冲串被引导到输出端，用于在所述输出端创建完整的数据脉冲串。 只要接收端口能够接收输出脉冲串，就调度输出脉冲串。

公开(公告)号：US07573896B2

公开(公告)日：2009-08-11

申请号：US11250873

申请日：2005-10-14

申请人： Sibing Wang ,  Xiaoqian Zhang ,  Zhonghai Gan ,  Shubing Zhai

发明人： Sibing Wang ,  Xiaoqian Zhang ,  Zhonghai Gan ,  Shubing Zhai

IPC分类号： H04L12/28

CPC分类号： H04L47/10 ,  H04L47/12 ,  H04L47/17 ,  H04L47/26 ,  H04L47/29 ,  H04L47/30 ,  H04L49/352

摘要： A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.

摘要翻译： 已经公开了用于系统分组接口设备的通用接口，分组切换，超量预定，队列级联和逻辑标识优先级的方法和装置。

公开(公告)号：US20060083185A1

公开(公告)日：2006-04-20

申请号：US11250873

申请日：2005-10-14

申请人： Sibing Wang ,  Xiaoqian Zhang ,  Zhonghai Gan ,  Shubing Zhai

发明人： Sibing Wang ,  Xiaoqian Zhang ,  Zhonghai Gan ,  Shubing Zhai

IPC分类号： H04L5/22

CPC分类号： H04L47/10 ,  H04L47/12 ,  H04L47/17 ,  H04L47/26 ,  H04L47/29 ,  H04L47/30 ,  H04L49/352

摘要： A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.

公开(公告)号：US07940662B2

公开(公告)日：2011-05-10

申请号：US10861897

申请日：2004-06-04

申请人： Shubing Zhai ,  Yefei Sun ,  Xiaoqian Zhang ,  Zhonghai Gan

发明人： Shubing Zhai ,  Yefei Sun ,  Xiaoqian Zhang ,  Zhonghai Gan

IPC分类号： H04L12/26

CPC分类号： H04L29/06 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L49/103 ,  H04L69/324

摘要： Data received from a bursty interface is received on a burst-by-burst basis. Once a burst is received, it is stored in a processing queue. A complete burst is received so long a processing queue can accommodate a data burst. The complete data burst is directed to an output and used to create a complete data burst on said output. The output burst is dispatched so long as a receiving port is able to accept the output burst.

摘要翻译： 从突发接口接收的数据以突发为基础接收。 一旦接收到脉冲串，它就被存储在处理队列中。 接收到完整的脉冲串，处理队列可以容纳数据脉冲串。 完整的数据脉冲串被引导到输出端，用于在所述输出端创建完整的数据脉冲串。 只要接收端口能够接收输出脉冲串，就调度输出脉冲串。

公开(公告)号：US20060039284A1

公开(公告)日：2006-02-23

申请号：US11102996

申请日：2005-04-11

申请人： Shubing Zhai ,  Yefei Sun ,  Xiaoqian Zhang ,  Zhonghai Gan

发明人： Shubing Zhai ,  Yefei Sun ,  Xiaoqian Zhang ,  Zhonghai Gan

IPC分类号： H04J1/16

CPC分类号： H04L49/901 ,  H04L49/90

摘要： Disclosed are a method and apparatus for processing a complete burst of data by receiving said complete burst of data, storing the complete burst of data in a memory, associating the complete burst of data with a first logical channel and dispatching an egress burst of data according to one or more complete bursts of data stored in a memory and associated with the first logical channel.

摘要翻译： 公开了一种用于通过接收所述完整的数据突发来处理完整的数据突发的方法和装置，将完整的数据突发存储在存储器中，将完整的数据突发与第一逻辑信道相关联，并根据 到存储在存储器中并与第一逻辑信道相关联的一个或多个完整的数据脉冲串。