公开(公告)号：US08970419B2

公开(公告)日：2015-03-03

申请号：US13928798

申请日：2013-06-27

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

IPC: H03M1/34 ,  H03M1/12

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract translation: 一个模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

公开(公告)号：US09007096B1

公开(公告)日：2015-04-14

申请号：US14324858

申请日：2014-07-07

Applicant: Xilinx, Inc.

Inventor： Declan Carey ,  Thomas Mallard ,  Mark Smyth ,  James Hudner

IPC: H03K5/22 ,  G01R17/02

CPC classification number: H03K5/2481 ,  H03F3/45197 ,  H03F2200/78 ,  H03F2203/45674

Abstract: An apparatus relating generally to voltage conversion includes an amplifier coupled to receive an input voltage and a reference voltage. First and second converters are coupled to the amplifier to receive a bias voltage. The first converter includes a first transconductor coupled to receive the bias voltage to adjust a first tail current, and a first differential input. A first inverter of the first converter has a first feedback device coupled input-to-output to provide a first transimpedance amplifier load. The first inverter is coupled to the first transconductor. The second converter includes a second transconductor coupled to receive the bias voltage to adjust a second tail current, and a second differential input. A second inverter of the second converter has a second feedback device coupled input-to-output to provide a second transimpedance amplifier load. The second inverter is coupled to the second transconductor.

Abstract translation: 一般涉及电压转换的装置包括耦合以接收输入电压和参考电压的放大器。 第一和第二转换器耦合到放大器以接收偏置电压。 第一转换器包括耦合以接收偏置电压以调整第一尾电流的第一跨导器和第一差分输入。 第一转换器的第一反相器具有耦合输入到输出的第一反馈器件，以提供第一跨阻抗放大器负载。 第一反相器耦合到第一跨导器。 第二转换器包括耦合以接收偏置电压以调整第二尾电流的第二跨导器和第二差分输入。 第二转换器的第二反相器具有耦合输入到输出以提供第二跨阻放大器负载的第二反馈装置。 第二反相器耦合到第二跨导器。

公开(公告)号：US10454463B1

公开(公告)日：2019-10-22

申请号：US16107850

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： James Hudner

IPC: H03K5/24 ,  G06F1/3237 ,  G05F3/16 ,  G06F3/16

Abstract: Apparatus and associated methods relate to a dynamic quantizer circuit including a tail voltage supply magnitude (VTAIL) distinct from a general supply voltage (Avcc/Avss), VTAIL providing power to a tail clock buffer to generate tail clock signals to tail devices. In an illustrative example, a compensation processor may control a regulator producing a determined VTAIL value in response to one or more parametric signals, for example, the Avcc voltage value, a circuit temperature and a transistor speed process (TSP). The TSP signal may be determined, for example, by process-dependent circuit devices. The compensation processor may be, for example, configured to lower VTAIL in response to detecting a worst-case RMS noise corner, or to raise VTAIL in response to detecting a worst-case clock-to-q corner. Various adjustable VTAILs may be configured to continuously optimize RMS noise, offset and speed performance with low power consumption in various quantizers over process, voltage and/or temperature.

公开(公告)号：US20150002326A1

公开(公告)日：2015-01-01

申请号：US13928798

申请日：2013-06-27

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

Abstract: An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract translation: 公开了一种模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。