公开(公告)号：US20150002326A1

公开(公告)日：2015-01-01

申请号：US13928798

申请日：2013-06-27

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

Abstract: An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract translation: 公开了一种模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

公开(公告)号：US08970419B2

公开(公告)日：2015-03-03

申请号：US13928798

申请日：2013-06-27

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

IPC: H03M1/34 ,  H03M1/12

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract translation: 一个模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

公开(公告)号：US08766832B1

公开(公告)日：2014-07-01

申请号：US13669033

申请日：2012-11-05

Applicant: Xilinx, Inc.

Inventor： Ivan Bogue

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/10 ,  H03M1/1004 ,  H03M1/1014 ,  H03M1/12 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) includes an analog input stage including an output configured to generate an analog output signal and a digital stage coupled the output of the analog input stage. The digital stage is configured to classify the analog output signal into one of a plurality of consecutive voltage ranges. Responsive to the analog output signal being classified in a first enumerated voltage range of the plurality of voltage ranges during a rotation of a sample, a voltage for a subsequent rotation is determined as if the analog output signal is classified into a non-enumerated voltage range selected according to a state of a random number signal.

Abstract translation: 模数转换器（ADC）包括模拟输入级，其包括被配置为产生模拟输出信号的输出和耦合模拟输入级的输出的数字级。 数字级被配置为将模拟输出信号分类为多个连续电压范围之一。 响应于模拟输出信号被分类为在样品旋转期间的多个电压范围的第一枚举电压范围中，用于随后旋转的电压被确定为仿照模拟输出信号被分类为非枚举电压范围 根据随机数信号的状态选择。

公开(公告)号：US09000800B1

公开(公告)日：2015-04-07

申请号：US13621655

申请日：2012-09-17

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  Edward Cullen ,  Ivan Bogue

IPC: H03K17/16 ,  H03K19/00 ,  H03K19/003 ,  H04L25/02

CPC classification number: H03K19/0005 ,  H03K19/00384 ,  H04L25/0278

Abstract: A system for calibrating impedance of an input/output (I/O) buffer on a semiconductor die includes: the I/O buffer; a temperature sensor on the semiconductor die; and a supply sensor on the semiconductor die. The temperature sensor is configured to acquire temperature information for calibrating the I/O buffer. The supply sensor is configured to acquire voltage information for calibrating the I/O buffer. The I/O buffer comprises: a memory component coupled to the temperature and supply sensors and configured to store the acquired temperature or voltage information; a logic component coupled to the memory component; and a driver with driver legs. The driver is coupled to the logic component. The logic component is configured to generate driver control signals representing an on/off configuration for the driver legs of the driver based at least in part on the acquired temperature information or the acquired voltage information stored in the memory component.

Abstract translation: 用于校准半导体管芯上的输入/输出（I / O）缓冲器的阻抗的系统包括：I / O缓冲器; 半导体管芯上的温度传感器; 以及半导体管芯上的供应传感器。 温度传感器被配置为获取用于校准I / O缓冲器的温度信息。 供电传感器被配置为获取用于校准I / O缓冲器的电压信息。 I / O缓冲器包括：耦合到温度和电源传感器并被配置为存储获取的温度或电压信息的存储器组件; 耦合到存储器组件的逻辑组件; 和一个司机与司机腿。 驱动器耦合到逻辑组件。 逻辑部件被配置为至少部分地基于所获取的温度信息或存储在存储器部件中的所获取的电压信息来生成表示驾驶员的驾驶员腿的开/关配置的驾驶员控制信号。