公开(公告)号：US11709522B1

公开(公告)日：2023-07-25

申请号：US17023016

申请日：2020-09-16

Applicant: XILINX, INC.

Inventor： Sebastian Turullols ,  Ravinder Sharma ,  Siva Santosh Kumar Pyla ,  Raj Kumar Rampelli ,  Deboleena Minz Sakalley ,  Nilay Shah

IPC: G06F1/26 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/26

Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

公开(公告)号：US20230055704A1

公开(公告)日：2023-02-23

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram PVSS ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US11720735B2

公开(公告)日：2023-08-08

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram Pvss ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/3953

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F30/3953

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US11507394B1

公开(公告)日：2022-11-22

申请号：US17408152

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Gokul Kavungal Nechikott ,  Saifuddin Kaijar ,  Brian S. Martin ,  Suraj Patel ,  Rishabh Gupta ,  Ch Vamshi Krishna ,  Kaustuv Manji

IPC: G06F9/445 ,  G06F9/4401 ,  G06F13/42

Abstract: Changing accelerator card images without rebooting a host system includes receiving, within an integrated circuit (IC) of an accelerator card, an address of a platform image stored in a non-volatile memory of the accelerator card. The address is received over a communication link between the host system and the accelerator card while the communication link is connected. Changing accelerator card images includes detecting, within a register of the IC, that a warm boot enable flag is set and that the communication link with the host system is disconnected. In response to detecting that the warm boot enable flag is set and that the communication link is disconnected, loading of the platform image from the address of the non-volatile memory into the integrated circuit is initiated.