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    Method to form CoSi.sub.2 on shallow junction by Si implantation
    1.
    发明授权
    Method to form CoSi.sub.2 on shallow junction by Si implantation 有权
    通过Si注入在浅结上形成CoSi2的方法

    公开(公告)号：US6096647A

    公开(公告)日：2000-08-01

    申请号：US425311

    申请日：1999-10-25

    申请人： Hong Yang ,  Xing Yu ,  Ying Keung Leung

    发明人： Hong Yang ,  Xing Yu ,  Ying Keung Leung

    IPC分类号： H01L21/285 ,  H01L21/44

    CPC分类号： H01L21/28518

    摘要： A new method for forming a cobalt disilicide film on shallow junctions with reduced silicon consumption in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the semiconductor substrate and subjected to a first rapid thermal process whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer is removed. A dielectric layer is deposited overlying the substrate and the cobalt monosilicide layer. Silicon ions are implanted through the dielectric layer into the cobalt monosilicide layer. The substrate is subjected to a second rapid thermal process whereby the cobalt monosilicide is transformed to cobalt disilicide wherein the silicon ions implanted into the cobalt monosilicide layer act as a main (not sole) silicon source for the transformation to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

    摘要翻译： 描述了在制造集成电路中减少硅消耗的浅结上形成二硅化硅膜的新方法。 提供具有要被硅化的硅区域的半导体衬底。 将钴层沉积在半导体衬底上并进行第一快速热处理，由此将钴转化为一钴硅酸盐，其中它覆盖在硅区域上，并且其中不覆盖硅区域的钴是未反应的。 去除未反应的钴层。 沉积在衬底和单硅化钴层上的电介质层。 通过介电层将硅离子注入到单硅化钴层中。 对衬底进行第二快速热处理，由此将一价硅酸钴转化为二硅化钴，其中注入到一钴硅化物层中的硅离子用作主要（非唯一的）硅源，以完成二硅化硅膜的形成 在制造集成电路。

    Method of fabrication of a raised source/drain transistor
    2.
    发明授权
    Method of fabrication of a raised source/drain transistor 有权
    凸起源极/漏极晶体管的制造方法

    公开(公告)号：US6100161A

    公开(公告)日：2000-08-08

    申请号：US442494

    申请日：1999-11-18

    申请人： Xing Yu ,  Ying Keung Leung ,  Hong Yang ,  Shyue Fong Quek

    发明人： Xing Yu ,  Ying Keung Leung ,  Hong Yang ,  Shyue Fong Quek

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/4763

    CPC分类号： H01L29/66606 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

    摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions. Source/drain regions are formed in the active area under the sidewall spacers and under the polysilicon portions. A salicide portion is formed over the gate conductor and salicide portions are formed over the polysilicon portions, whereby the formation of the salicide layers over the polysilicon portions consumes a portion of the polysilicon portions leaving the remainder of the polysilicon layers to form shallow source/drain junctions underneath the polysilicon portion salicide portions.

    摘要翻译： 一种制造晶体管的方法，包括以下步骤。 提供了在有源区内具有衬垫氧化物部分的硅半导体衬底。 多晶硅层沉积在硅半导体衬底上并在衬垫氧化物部分上方。 在多晶硅层上沉积焊盘氧化物层。 在有源区域的两侧形成浅的隔离沟槽区域。 去除衬垫氧化物层。 在衬垫氧化物部分上蚀刻并除去多晶硅层，留下衬垫氧化物部分和浅隔离沟槽区域之间的多晶硅部分。 焊盘氧化物部分被栅氧化物部分代替。 具有暴露的侧壁的栅极导体形成在栅极氧化物部分上方和多晶硅部分之间。 侧壁间隔件形成在栅极导体的暴露的侧壁上，其中侧壁间隔件与多晶硅部分接触。 源极/漏极区域形成在侧壁间隔下方的有源区域和多晶硅部分下方。 在栅极导体上形成自对准硅化物部分，并且在多晶硅部分上形成自对准硅化物部分，由此在多晶硅部分上形成硅化物层消耗部分多晶硅部分留下剩余的多晶硅层以形成浅的源极/漏极 在多晶硅部分自对准硅化物部分下方的结。

    Method for forming a raised source and drain without using selective epitaxial growth
    3.
    发明授权
    Method for forming a raised source and drain without using selective epitaxial growth 有权
    在不使用选择性外延生长的情况下形成升高的源极和漏极的方法

    公开(公告)号：US06090691A

    公开(公告)日：2000-07-18

    申请号：US439366

    申请日：1999-11-15

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/22

    CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L21/2255 ,  H01L29/665

    摘要： A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

    摘要翻译： 一种用于在不使用选择性外延硅生长的情况下形成隆起的源极和漏极结构的方法。 提供具有被介电结构覆盖的一个或多个栅极区域的半导体衬底。 掺杂的多晶硅结构与每一侧上的电介质结构相邻，并且与来自CMP工艺的电介质结构共面。 去除第一电介质结构以形成栅极开口，并且在栅极开口的底部和侧壁上形成衬里氧化物层。 在栅极开口的侧壁上的衬垫氧化物层上形成介质间隔物，并且从栅极开口的底部和掺杂的多晶硅结构上方移除衬里氧化物层。 通过从掺杂多晶硅层扩散杂质离子，在半导体衬底中形成源区和漏区。 在半导体结构上形成栅极氧化物层和栅极多晶硅层，并且平坦化栅极多晶硅层以形成栅电极。 在关键步骤中，去除电介质间隔物以形成间隔开口，并通过间隔开孔注入杂质离子并退火以形成源极和漏极延伸部分。 电介质间隔物被重整，并且在掺杂多晶硅结构和栅电极上形成自对准的硅化物层。 或者，可以在去除电介质间隔物和注入离子以形成源极和漏极延伸部之前形成自对准硅化物层。

    Method to form a self-aligned CMOS inverter using vertical device integration
    4.
    发明授权
    Method to form a self-aligned CMOS inverter using vertical device integration 失效
    使用垂直器件集成形成自对准CMOS反相器的方法

    公开(公告)号：US06747314B2

    公开(公告)日：2004-06-08

    申请号：US10242483

    申请日：2002-09-12

    申请人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

    发明人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

    IPC分类号： H01L2976

    CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

    摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

    摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

    Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge
    5.
    发明授权
    Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge 失效
    通过在栅极边缘形成微动开关来形成低重叠电容晶体管的方法

    公开(公告)号：US06417056B1

    公开(公告)日：2002-07-09

    申请号：US09981439

    申请日：2001-10-18

    申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    IPC分类号： H01L21336

    CPC分类号： H01L29/66636 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834

    摘要： A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.

    摘要翻译： 描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。 栅电极被设置在衬底上的栅介电层上，并且在其上具有硬掩模层。 在衬底上形成氧化物层。 第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。 源/漏扩展被植入。 第二间隔件形成在第一间隔件上。 源极/漏极区域被植入。 沉积覆盖在栅电极和氧化物层上的介电层，并且平坦化到硬掩模层，由此使第一和第二间隔物暴露。 去除暴露的第二间隔物和下面的氧化物层。 蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。 微通孔填充有外延氧化物层并且平坦化到硬掩模层。 图案化电介质层以在外延氧化物层上形成第三间隔物。 微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数，以完成具有低重叠电容的晶体管的形成。

    Method for forming a transistor gate dielectric with high-K and low-K regions
    6.
    发明授权
    Method for forming a transistor gate dielectric with high-K and low-K regions 有权
    用于形成具有高K和低K区的晶体管栅极电介质的方法

    公开(公告)号：US06406945B1

    公开(公告)日：2002-06-18

    申请号：US09769810

    申请日：2001-01-26

    申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

    发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

    IPC分类号： H01L21335

    CPC分类号： H01L29/517 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66583 ,  Y10S257/90

    摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

    摘要翻译： 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成虚拟电介质层。 图案化虚拟介质层以形成栅极开口。 在虚拟电介质上和栅极开口中形成高K电介质层。 在高K电介质层上形成低K电介质层。 在栅极开口边缘的低K电介质层上形成间隔物。 低K电介质层从间隔物之间​​的栅极开口的底部去除。 移除间隔件以形成阶梯式门开口。 阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层 开门 在阶梯式门开口形成栅电极。

    Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner
    8.
    发明授权
    Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 有权
    通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法

    公开(公告)号：US06468877B1

    公开(公告)日：2002-10-22

    申请号：US09907651

    申请日：2001-07-19

    申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

    发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

    IPC分类号： H01L2176

    CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

    摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

    摘要翻译： 一种制造半导体器件的气隙间隔物的方法，包括以下步骤。 提供具有至少一对限定有源区域的STI的半导体衬底。 在有源区内的基板上形成栅电极。 栅电极具有底层栅介电层。 在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。 在衬垫氧化物层上形成衬里氮化物层。 在结构上形成厚的氧化物层。 厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。 用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。 在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。 蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。 栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

    Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)
    9.
    发明授权
    Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
    通过SiGe或多量子阱（MQW）的选择性沉积形成非常高迁移率的垂直沟道晶体管的方法

    公开(公告)号：US06455377B1

    公开(公告)日：2002-09-24

    申请号：US09765040

    申请日：2001-01-19

    申请人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

    发明人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

    IPC分类号： H01L21336

    CPC分类号： H01L29/66666 ,  H01L29/1054 ,  H01L29/66916 ,  H01L29/7827 ,  H01L29/802

    摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

    摘要翻译： 一种制造垂直沟道晶体管的方法，包括以下步骤。 提供具有上表面的半导体衬底。 在半导体衬底上形成高掺杂N型下部外延硅层。 在下部外延硅层上形成低掺杂P型中间外延硅层。 在中间外延硅层上形成高掺杂N型上部外延硅层。 蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。 在隔离槽内形成氧化物。 氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。 在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。 在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。 栅极导体层形成在栅极电介质层上，填充栅极沟槽。