利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.039 秒)

    Semiconductor device having additive latency
    3.
    发明授权
    Semiconductor device having additive latency 有权
    具有附加延迟的半导体器件

    公开(公告)号：US08358546B2

    公开(公告)日：2013-01-22

    申请号：US12945521

    申请日：2010-11-12

    申请人： Yang-ki Kim ,  Jung-hwan Choi

    发明人： Yang-ki Kim ,  Jung-hwan Choi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2272

    摘要： A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.

    摘要翻译： 半导体器件接收对应于存储器访问操作的命令，并在附加等待时间之后执行存储器存取操作。 当接收到命令时，加法等待时间开始。 该半导体器件包括用于控制时钟信号的相位并输出相位控制的时钟信号的相位控制器，以及用于产生和输出控制信号的控制器，用于使得能够在加法器中的预定时间禁用相位控制器 潜伏期

    Data receiving apparatus using semi-dual reference voltage
    4.
    发明授权
    Data receiving apparatus using semi-dual reference voltage 有权
    采用半双参考电压的数据接收装置

    公开(公告)号：US07518411B2

    公开(公告)日：2009-04-14

    申请号：US11747685

    申请日：2007-05-11

    申请人： Yang-ki Kim ,  Young-jin Jeon

    发明人： Yang-ki Kim ,  Young-jin Jeon

    IPC分类号： G01R19/00

    CPC分类号： H04L25/0292

    摘要： A semi-dual reference voltage data receiving apparatus includes a first input buffer, a second input buffer, and a phase detector wherein the first input buffer includes a first input receiving unit, a first sense amplifier, and a first current offset controlling unit. The first sense amplifier senses and amplifies the voltage difference between the voltage of a first terminal of a first input transistor and the voltage of a first terminal of a second input transistor. The first current offset controlling unit controls the offset of the current that flows through the second terminal of the second input transistor.

    摘要翻译： 半双参考电压数据接收装置包括第一输入缓冲器，第二输入缓冲器和相位检测器，其中第一输入缓冲器包括第一输入接收单元，第一读出放大器和第一电流偏移控制单元。 第一读出放大器感测并放大第一输入晶体管的第一端子的电压与第二输入晶体管的第一端子的电压之间的电压差。 第一电流偏移控制单元控制流过第二输入晶体管的第二端子的电流的偏移。

    Delay-locked loop circuit controlled by column strobe write latency
    5.
    发明授权
    Delay-locked loop circuit controlled by column strobe write latency 失效
    延迟锁定环路电路由列选通写入延迟控制

    公开(公告)号：US08049545B2

    公开(公告)日：2011-11-01

    申请号：US12644044

    申请日：2009-12-22

    申请人： Yang-ki Kim ,  Seok-hun Hyun

    发明人： Yang-ki Kim ,  Seok-hun Hyun

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03K2005/00026 ,  H03K2005/0011 ,  H03K2005/00202 ,  H03K2005/00208

    摘要： The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.

    摘要翻译： DLL电路包括根据外部输入的列地址选通写入延迟（CWL）信号来控制单位延迟电路的偏置电流的控制电路，和/或DCC控制电路，其调节DCC的DCC电流的步长，根据 外部输入列地址选通写入延迟（CWL）信号。 CWL信号可以由半导体存储器件输入，并且可以指示列地址选通写入半导体存储器件的延迟。 半导体存储器件可以是双倍数据速率（DDR）同步DRAM（SDRAM）器件。

    On-die termination latency clock control circuit and method of controlling the on-die termination latency clock
    6.
    发明授权
    On-die termination latency clock control circuit and method of controlling the on-die termination latency clock 有权
    片上终端延迟时钟控制电路和控制片上终端等待时钟的方法

    公开(公告)号：US08035412B2

    公开(公告)日：2011-10-11

    申请号：US12754043

    申请日：2010-04-05

    申请人： Chul-hwan Choo ,  Jun-bae Kim ,  Yang-ki Kim ,  Jun-ho Shin

    发明人： Chul-hwan Choo ,  Jun-bae Kim ,  Yang-ki Kim ,  Jun-ho Shin

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： G11C7/1051 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272

    摘要： A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.

    摘要翻译： 半导体器件包括片上终端（ODT）等待时钟控制电路和由ODT等待时钟控制电路控制的ODT电路。 ODT等待时钟控制电路包括ODT使能信号发生器，其接收通过ODT电路的ODT焊盘输入的ODT信号，并产生ODT使能信号;以及ODT等待时钟发生器，响应于所述ODT等待时间产生多个ODT等待时间 ODT使能信号。 ODT使能信号包括第一逻辑电平的使能周期和第二和不同逻辑电平的禁用周期，并且ODT使能信号发生器通过将使能周期的宽度增加预定时钟周期来产生ODT使能信号，并且 只在增加的使能期间产生时钟。

    Semiconductor devices having ZQ calibration circuits and calibration methods thereof
    7.
    发明授权
    Semiconductor devices having ZQ calibration circuits and calibration methods thereof 有权
    具有ZQ校准电路的半导体器件及其校准方法

    公开(公告)号：US07969182B2

    公开(公告)日：2011-06-28

    申请号：US12656587

    申请日：2010-02-04

    申请人： Jun-bae Kim ,  Yang-ki Kim

    发明人： Jun-bae Kim ,  Yang-ki Kim

    IPC分类号： H03K19/003

    CPC分类号： H03K19/0005 ,  G11C7/02 ,  G11C7/04 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

    摘要： Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a calibration circuit for performing a pull-down calibration operation in response to a pull-down calibration enable signal and a command control unit for generating the pull-down calibration enable signal in response to a DLL reset signal. The calibration method includes adjusting an impedance of a first pull-up resistance structure in response to pull-up calibration codes having a default value. A pull-down calibration enable signal may be generated in response to a DLL reset signal. A voltage of the first node and a reference voltage are compared by a comparator. The comparator outputs pull-down calibration codes based on the comparison. An impedance of a pull-down resistance structure is adjusted, so a resistance of the pull-down resistance structure is equal to a resistance of the first pull-up resistance structure.

    摘要翻译： 提供了一种用于在没有外部ZQ校准命令的情况下执行校准操作的半导体器件及其校准方法。 半导体器件包括用于响应于下拉校准使能信号执行下拉校准操作的校准电路和用于响应于DLL复位信号产生下拉校准使能信号的命令控制单元。 校准方法包括响应于具有默认值的上拉校准码来调整第一上拉电阻结构的阻抗。 可以响应于DLL复位信号而产生下拉校准使能信号。 比较器比较第一节点的电压和参考电压。 比较器根据比较器输出下拉校准代码。 调整下拉电阻结构的阻抗，因此下拉电阻结构的电阻等于第一上拉电阻结构的电阻。

    DELAY-LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN STROBE WRITE LATENCY
    8.
    发明申请
    DELAY-LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN STROBE WRITE LATENCY 失效
    延迟锁定循环电路由柱控制写入时间控制

    公开(公告)号：US20100156488A1

    公开(公告)日：2010-06-24

    申请号：US12644044

    申请日：2009-12-22

    申请人： Yang-ki Kim ,  Seok-hun Hyun

    发明人： Yang-ki Kim ,  Seok-hun Hyun

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03K2005/00026 ,  H03K2005/0011 ,  H03K2005/00202 ,  H03K2005/00208

    摘要： The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.

    摘要翻译： DLL电路包括根据外部输入的列地址选通写入延迟（CWL）信号来控制单位延迟电路的偏置电流的控制电路，和/或DCC控制电路，其调节DCC的DCC电流的步长，根据 外部输入列地址选通写入延迟（CWL）信号。 CWL信号可以由半导体存储器件输入，并且可以指示列地址选通写入半导体存储器件的延迟。 半导体存储器件可以是双倍数据速率（DDR）同步DRAM（SDRAM）器件。

    Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads
    9.
    发明申请
    Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads 有权
    半导体存储器件具有用于补偿数据输入 - 输出焊盘的寄生电阻的驱动器

    公开(公告)号：US20100110749A1

    公开(公告)日：2010-05-06

    申请号：US12461141

    申请日：2009-08-03

    申请人： Hae-young Chung ,  Yang-ki Kim ,  Seok-woo Choi

    发明人： Hae-young Chung ,  Yang-ki Kim ,  Seok-woo Choi

    IPC分类号： G11C5/06 ,  H01S4/00 ,  G11C8/08

    CPC分类号： G11C5/063 ,  G11C8/08 ,  Y10T29/49002

    摘要： A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.

    摘要翻译： 一种半导体存储器件，包括电源电压焊盘，接地电压焊盘以及布置在电源电压焊盘和接地电压焊盘之间的至少两个数据输入/输出焊盘。 半导体存储器件具有第一上拉驱动器，其连接到位于与电源电压焊盘相距第一距离处的第二数据输入/输出焊盘，以及第一下拉驱动器，其连接到第一数据输入/输出 焊盘位于离地电压焊盘的第二距离处。

    Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads
    10.
    发明授权
    Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads 有权
    半导体存储器件具有用于补偿数据输入 - 输出焊盘的寄生电阻的驱动器

    公开(公告)号：US08203860B2

    公开(公告)日：2012-06-19

    申请号：US12461141

    申请日：2009-08-03

    申请人： Hae-young Chung ,  Yang-ki Kim ,  Seok-woo Choi

    发明人： Hae-young Chung ,  Yang-ki Kim ,  Seok-woo Choi

    IPC分类号： G11C5/06 ,  H01S4/00 ,  G11C8/08

    CPC分类号： G11C5/063 ,  G11C8/08 ,  Y10T29/49002

    摘要： A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.

    摘要翻译： 一种半导体存储器件，包括电源电压焊盘，接地电压焊盘以及布置在电源电压焊盘和接地电压焊盘之间的至少两个数据输入/输出焊盘。 半导体存储器件具有第一上拉驱动器，其连接到位于与电源电压焊盘相距第一距离处的第二数据输入/输出焊盘，以及第一下拉驱动器，其连接到第一数据输入/输出 焊盘位于离地电压焊盘的第二距离处。