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公开(公告)号：US11901023B2
公开(公告)日：2024-02-13
申请号：US17945783
申请日：2022-09-15
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Changhyun Lee , Xiangnan Zhao , Haibo Li
CPC classification number: G11C16/3459 , G11C16/0433 , G11C16/10 , G11C16/26 , G11C16/30
Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.
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公开(公告)号：US11887671B2
公开(公告)日：2024-01-30
申请号：US17518783
申请日：2021-11-04
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Haibo Li , Joohyun Jin , Chao Zhang
CPC classification number: G11C16/102 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3404
Abstract: A method for programming a three-dimensional (3D) memory device is provided. The 3D memory device has a plurality of memory strings with memory cells vertically stacked, and each memory cell is addressable through a word line and a bit line. The method for programming the 3D memory device includes the following steps: applying a program voltage on a selected word line; applying a first pass voltage on a first group of unselected word lines; and applying a second pass voltage on a second group of unselected word lines, wherein the second pass voltage is different from the first pass voltage.
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公开(公告)号：US20240006004A1
公开(公告)日：2024-01-04
申请号：US18225575
申请日：2023-07-24
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Haibo Li , Man Lung Mui , Yu Wang
CPC classification number: G11C16/3486 , G11C16/08 , G11C16/3459
Abstract: In certain aspects, a memory device includes a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The plurality of memory cells includes a first set of memory cells configured to be programmed into a first set of programming states each of which is not lower than a first predetermined programming state. The control circuit is configured to perform a first program pass on the first set of memory cells. The control circuit is configured to continue to program at least a first memory cell from the first set of memory cells with one or more first programming voltages. A threshold voltage of the first memory cell is greater than a first verification voltage that corresponds to a first programming state of the first memory cell. The control circuit is configured to perform a second program pass on the first set of memory cells.
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公开(公告)号：US11705202B2
公开(公告)日：2023-07-18
申请号：US17499154
申请日：2021-10-12
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Zhipeng Dong , Venkatagirish Nagavarapu , Haibo Li
CPC classification number: G11C16/10 , G11C16/3459
Abstract: A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.
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公开(公告)号：US11468957B2
公开(公告)日：2022-10-11
申请号：US17191768
申请日：2021-03-04
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Changhyun Lee , Xiangnan Zhao , Haibo Li
Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.
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Patent Agency Ranking
公开(公告)号：US20210366552A1
公开(公告)日：2021-11-25
申请号：US17187690
申请日：2021-02-26
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Zhi Chao Du , Yu Wang , Haibo Li , Ke Jiang , Ye Tian
Abstract: A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.
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公开(公告)号：US20210183457A1
公开(公告)日：2021-06-17
申请号：US17187672
申请日：2021-02-26
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Haibo Li , Qiang Tang
Abstract: A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.
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8.发明申请公开(公告)号：US20200312417A1
公开(公告)日：2020-10-01
申请号：US16404744
申请日：2019-05-07
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Haibo Li , Chao Zhang , Yanxia Lin
Abstract: Programming in a non-volatile memory device includes applying at least one programming pulse to a non-volatile memory cell during a first programming loop; applying at least one programming pulse to the non-volatile memory cell during a second programming loop succeeding the first programming loop; and providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in the first programming loop with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the second programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.
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公开(公告)号：US20200265904A1
公开(公告)日：2020-08-20
申请号：US16371130
申请日：2019-04-01
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Haibo Li , Man Lung Mui
Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.
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公开(公告)号：US12205652B2
公开(公告)日：2025-01-21
申请号：US18090454
申请日：2022-12-28
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Xiaojiang Guo , Chao Zhang , Haibo Li
Abstract: A method for reading a memory device is provided. The memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages. The method includes: defining at least one read offset for each of the multi-level preset read voltages respectively, selecting at least one of the multi-level preset read voltages as at least one sampling voltage, reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell, and setting at least one offset flag, each representing a size of a respective one of at least one read offset, according to a sampling reading value of each of the at least one sampling voltage.
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