公开(公告)号：US07259058B2

公开(公告)日：2007-08-21

申请号：US10020314

申请日：2001-12-18

申请人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Satoshi Yamamoto ,  Toshihide Nabatame ,  Toshio Ando ,  Hiroshi Sakuma ,  Shinpei Iijima

发明人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Satoshi Yamamoto ,  Toshihide Nabatame ,  Toshio Ando ,  Hiroshi Sakuma ,  Shinpei Iijima

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/28568 ,  H01L28/55 ,  H01L28/91

摘要： A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

摘要翻译： 通过化学气相沉积法形成氧气污染少，热稳定性高的钌电极。 在使用有机钌化合物作为前体的化学气相沉积方法中，氧化气体的引入限于当前体供应时，并且允许反应在低氧分压下发生。 因此，可以形成氧含量低的钌膜。 此外，在形成钌膜之后，进行不低于形成温度的退火，由此形成热稳定性高的钌膜。

公开(公告)号：US06992022B2

公开(公告)日：2006-01-31

申请号：US10795430

申请日：2004-03-09

申请人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Toshihide Nabatame

发明人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Toshihide Nabatame

IPC分类号： H01L21/31

CPC分类号： H01L28/60 ,  C23C16/18 ,  C23C16/409 ,  H01L21/28556 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/55

摘要： A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

公开(公告)号：US06989304B1

公开(公告)日：2006-01-24

申请号：US10297811

申请日：2000-08-11

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Toshihide Nabatame

IPC分类号： H01L21/8242

CPC分类号： C23C14/046 ,  C23C14/165 ,  C23C16/18 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/91

摘要： In the method of manufacturing a semiconductor device according to this invention, when an interlayer insulating film is fabricated such that an opening is cylindrical and low-pressure and long-throw sputtering is used for forming a lower ruthenium electrode, a ruthenium film can be deposited on the side wall of a deep hole. Further, after removing the ruthenium film deposited on the upper surface of the interlayer insulating film, a dielectric material comprising, for example, a tantalum pentoxide film is deposited. Successively, an upper ruthenium electrode is deposited using, for example, Ru(EtCp)2 as a starting material and by chemical vapor deposition of conveying the starting material by bubbling. The upper ruthenium electrode can be formed with good coverage by using conditions that the deposition rate of the ruthenium film depends on the formation temperature (reaction controlling condition). This invention can provide a fine concave type capacitor having a ruthenium electrode.

摘要翻译： 在根据本发明的半导体器件的制造方法中，当制造使得开口为圆柱形的层间绝缘膜并且使用低压和长距离溅射来形成下部钌电极时，可以沉积钌膜 在一个深孔的侧壁上。 此外，在除去沉积在层间绝缘膜的上表面上的钌膜之后，沉积包括例如五氧化二钽膜的电介质材料。 接着，使用例如Ru（EtCp）2 N 2作为起始材料并通过化学气相沉积，通过鼓泡输送起始材料来沉积上钌电极。 通过使用钌膜的沉积速率取决于形成温度（反应控制条件）的条件，可以形成具有良好覆盖度的上钌电极。 本发明可以提供一种具有钌电极的细凹型电容器。

公开(公告)号：US06521494B2

公开(公告)日：2003-02-18

申请号：US10211569

申请日：2002-08-05

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

公开(公告)号：US06503791B2

公开(公告)日：2003-01-07

申请号：US09767706

申请日：2001-01-24

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film.

摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。

公开(公告)号：US06743739B2

公开(公告)日：2004-06-01

申请号：US10101600

申请日：2002-03-21

申请人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Toshihide Nabatame

发明人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Toshihide Nabatame

IPC分类号： H01L2131

CPC分类号： H01L28/60 ,  C23C16/18 ,  C23C16/409 ,  H01L21/28556 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/55

摘要： A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

公开(公告)号：US06555429B2

公开(公告)日：2003-04-29

申请号：US09810627

申请日：2001-03-19

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

公开(公告)号：US06483143B2

公开(公告)日：2002-11-19

申请号：US09810401

申请日：2001-03-19

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L27108

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。 在预定温度下在下电极和防沉积膜上形成电介质膜。 即使暴露在用于形成电介质膜的预定温度下，下电极的材料也不会导通。 上电极进一步形成在电介质膜上。 上下电极和氧化物介质膜一起构成存储单元的电容器。

公开(公告)号：US07772678B2

公开(公告)日：2010-08-10

申请号：US12333577

申请日：2008-12-12

申请人： Kunihiko Iwamoto ,  Koji Tominaga ,  Toshihide Nabatame ,  Tomoaki Nishimura

发明人： Kunihiko Iwamoto ,  Koji Tominaga ,  Toshihide Nabatame ,  Tomoaki Nishimura

IPC分类号： H01L23/58 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.

摘要翻译： 在清洁基板的表面之后，形成界面层或反扩散膜。 在抗扩散膜上构建金属氧化物膜。在NH 3气氛中进行退火，以便在金属氧化物膜中扩散氮。 金属氧化物膜的构建和氮的扩散重复几次，随后在O 2气氛中进行退火。 通过在高于650℃的温度下在O 2气氛中退火该膜，可以控制金属氧化物膜中的漏电流。

公开(公告)号：US07618855B2

公开(公告)日：2009-11-17

申请号：US11540506

申请日：2006-10-02

申请人： Masaru Kadoshima ,  Toshihide Nabatame

发明人： Masaru Kadoshima ,  Toshihide Nabatame

IPC分类号： H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/6659

摘要： A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.

摘要翻译： 一种能够通过由金属硅化物膜形成的栅电极在MISFET的制造工艺中提高产量的技术。 在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成由多晶硅膜形成的硅栅电极。 然后，在形成氧化硅膜以覆盖硅栅电极之后，通过CMP抛光氧化硅膜的表面，从而暴露硅栅电极的表面。 随后，在氧化硅膜上形成图案化的绝缘膜。 此后，在氧化硅膜和绝缘膜上形成粘合膜。 然后，在粘合膜上形成镍膜。 此后，通过粘合膜在硅栅电极和镍膜之间发生硅化物反应。