公开(公告)号：US4599521A

公开(公告)日：1986-07-08

申请号：US453113

申请日：1982-12-27

申请人： Yasunori Kanai ,  Eiji Sugiyama ,  Kazumasa Nawata

发明人： Yasunori Kanai ,  Eiji Sugiyama ,  Kazumasa Nawata

IPC分类号： G05F3/22 ,  H03K19/086 ,  H03K19/003 ,  H03K19/092 ,  H03K19/098

CPC分类号： H03K19/086 ,  G05F3/22 ,  G05F3/227

摘要： A bias circuit for providing a reference voltage to an output circuit, for example, an ECL circuit in an LSI. The bias circuit is able to operate at a lower power supply voltage of about -2 V and includes a first transistor having an emitter which is connected to a power supply and a base and a collector commonly connected through an impedance circuit to ground. The bias circuit is also connected to the output circuit, whereby heat generation in the LSI is decreased.

摘要翻译： 用于向输出电路提供参考电压的偏置电路，例如LSI中的ECL电路。 偏置电路能够在约-2V的较低电源电压下工作，并且包括具有连接到电源的发射极的第一晶体管，以及通过阻抗电路共同连接到地的基极和集电极。 偏置电路也连接到输出电路，由此降低LSI中的发热。

公开(公告)号：US4866303A

公开(公告)日：1989-09-12

申请号：US676836

申请日：1984-11-30

申请人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu

发明人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu

IPC分类号： H03K19/003 ,  H03K19/086 ,  H03K19/173

CPC分类号： H03K19/00353 ,  H03K19/086 ,  H03K19/1735

摘要： An ECL gate array comprising a plurality of basic cells. Each basic cell has a pair of emitter-coupled transistors, and a load connected between the collectors of the transistors and a power supply line. In accordance with a circuit design information, the resistance value of the load can be selected for increasing a noise margin of the output logic levels without deteriorating the switching speed.

摘要翻译： 包括多个基本单元的ECL门阵列。 每个基本单元具有一对发射极耦合晶体管，以及连接在晶体管的集电极和电源线之间的负载。 根据电路设计信息，可以选择负载的电阻值，以增加输出逻辑电平的噪声容限，而不会降低开关速度。

公开(公告)号：US5144158A

公开(公告)日：1992-09-01

申请号：US511958

申请日：1990-04-17

申请人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Hiroki Yada ,  Taichi Saitoh ,  Toshiaki Sakai

发明人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Hiroki Yada ,  Taichi Saitoh ,  Toshiaki Sakai

IPC分类号： H03K3/013 ,  H03K3/037

CPC分类号： H03K3/013 ,  H03K3/0375

摘要： A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.

摘要翻译： 包括至少三个门电路的锁存电路和一个噪声电阻电路。 第一门电路（3,4,11,16）接收数据信号（DT）和时钟信号（CLK）。 第二门电路（1,7,13,17）连接到第一门电路的输出端。 第三门电路（2,5,12,18）在输入端接收第一反相时钟信号（＆amp; upbar＆C）。 第三门电路的第二输入端连接到第二门电路的输出，并且第一输出端连接到第二门电路的输入端，从而在第二和第三门之间形成反馈线 电路。 噪声电阻电路（8,9,20,21）在反馈线中至少具有信号延迟元件。 噪声电阻电路可以包括滤波电路。 噪声电阻电路还可以包括放大器电路。

公开(公告)号：US4918563A

公开(公告)日：1990-04-17

申请号：US316532

申请日：1989-02-27

申请人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Toshiaki Sakai

发明人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Toshiaki Sakai

IPC分类号： H03K19/086 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L29/00 ,  H03K19/003 ,  H03K19/173

CPC分类号： H03K19/00307 ,  H01L24/06 ,  H01L27/0248 ,  H01L27/11898 ,  H01L2224/05554

摘要： A semiconductor device such as an ECL gate array having emitter-follower-type output transistors, wherein protective elements are arranged between input/output pads and a power supply line connected to the collectors of the emitter-follower-type output transistors, whereby wiring between the protective elements and the power supply line become unnecessary so that the manufacturing process becomes easy and the integration degree is improved while a large tolerance voltage is maintained against destruction due to static electricity.

摘要翻译： 诸如具有发射极跟随器型输出晶体管的ECL门阵列的半导体器件，其中保护元件布置在输入/输出焊盘和连接到发射极跟随器型输出晶体管的集电极之间的电源线，由此在 保护元件和电源线变得不必要，使得制造过程变得容易，并且在保持大的公差电压以防止静电破坏的同时提高集成度。

公开(公告)号：US4678935A

公开(公告)日：1987-07-07

申请号：US650527

申请日：1984-09-14

申请人： Kazumasa Nawata ,  Yasunori Kanai

发明人： Kazumasa Nawata ,  Yasunori Kanai

IPC分类号： H01L21/822 ,  G05F3/22 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H03K19/00 ,  H03K19/086

CPC分类号： G05F3/22 ,  H03K19/086

摘要： An integrated circuit device having a simplified bias supply circuit for supplying bias power sources for a plurality of circuit units or cell units. The integrated circuit device cmprises: a cell unit array having a plurality of cell units disposed in a central portion of a semiconductor chip; a first power supply line and a second power supply line; and one or more common bias generating portions disposed at the periphery of the cell unit array, each of the common bias generating portions generating a single common bias voltage which differs from the potential of the second power supply line by a constant value. Each of the cell units comprises one or more logic circuit cells such as ECL type logic circuits, and an inner bias circuit which receives the common bias voltage and which generates a first inner bias voltage and a second inner bias voltage that are supplied to the respective logic circuit cell. The second inner bias voltage differs from the common bias voltage by a constant value, and the first inner bias voltage differs from the potential of the first power supply line at the cell unit by the value determined by the values of the elements in the inner bias circuit and by the common bias voltage.

摘要翻译： 一种具有用于为多个电路单元或单元单元提供偏置电源的简化偏置电源电路的集成电路装置。 集成电路装置包括：具有设置在半导体芯片的中心部分的多个单元单元的单元阵列阵列; 第一电源线和第二电源线; 以及设置在单元阵列阵列周边的一个或多个公共偏置产生部分，每个公共偏置产生部分产生与第二电源线的电位不同的单个公共偏置电压恒定值。 每个单元单元包括一个或多个逻辑电路单元，例如ECL型逻辑电路，以及内部偏置电路，其接收公共偏置电压，并产生提供给相应的第一内部偏置电压和第二内部偏置电压 逻辑电路单元。 第二内部偏置电压与公共偏置电压不同，并且第一内部偏置电压不同于单元单元处的第一电源线的电位由内部偏置中的元件的值确定的值 电路和公共偏置电压。

公开(公告)号：US4375999A

公开(公告)日：1983-03-08

申请号：US234198

申请日：1981-02-13

申请人： Kazumasa Nawata ,  Hirokazu Suzuki

发明人： Kazumasa Nawata ,  Hirokazu Suzuki

IPC分类号： H01L21/225 ,  H01L29/08 ,  H01L21/223

CPC分类号： H01L29/0804 ,  H01L21/2257 ,  Y10S438/923

摘要： A method of manufacturing a semiconductor device for simultaneously forming a plurality of diffused regions of selectively different diffusion depths, comprises forming polycrystalline semiconductor layers of corresponding, selectively different depths on the semiconductor substrate surface provided with a diffusion mask having a plurality of diffusion windows. By the impurity diffusion into the substrate through the windows at the polycrystalline semiconductor layer interface with the substrate, a comparatively shallow diffused region and a comparatively deep diffused region are formed simultaneously by a single diffusion process, respectively, under the comparatively thick polycrystalline semiconductor layer and the comparatively thin polycrystalline semiconductor layer.

摘要翻译： 一种用于同时形成选择性不同扩散深度的多个扩散区域的半导体器件的制造方法，包括在具有多个扩散窗口的扩散掩模的半导体衬底表面上形成相应的，选择性不同的深度的多晶半导体层。 通过在与衬底的多晶半导体层界面处的窗口中的杂质扩散到衬底中，在相对较厚的多晶半导体层下分别通过单个扩散工艺同时形成比较浅的扩散区域和相对较深的扩散区域，以及 相对薄的多晶半导体层。

公开(公告)号：US4278897A

公开(公告)日：1981-07-14

申请号：US974147

申请日：1978-12-28

申请人： Kenichi Ohno ,  Tohru Hosomizu ,  Kazumasa Nawata

发明人： Kenichi Ohno ,  Tohru Hosomizu ,  Kazumasa Nawata

IPC分类号： H01L23/528 ,  H01L27/118 ,  H01L27/00

CPC分类号： H01L27/11801 ,  H01L23/528 ,  H01L2924/0002

摘要： A large scale semiconductor integrated circuit device comprising plural transistors and resistors formed in one semiconductor substrate, and many emitter-coupled circuits formed by connecting the transistors and resistors with a double metallic layer on the substrate surface.Moreover, between the groups and respective input/output terminals, large scale transistors are provided for outputting the emitter-follower circuits. These groups containing the emitter coupled circuits are connected to the input/output terminals by the double metallic wiring layer.

摘要翻译： 一种大型半导体集成电路器件，包括形成在一个半导体衬底中的多个晶体管和电阻器，以及许多发射极耦合电路，其通过在衬底表面上用双金属层连接晶体管和电阻器而形成。 此外，在组与相应的输入/输出端子之间，提供用于输出发射极跟随器电路的大规模晶体管。 这些包含发射极耦合电路的组通过双金属布线层连接到输入/输出端子。

公开(公告)号：US5216296A

公开(公告)日：1993-06-01

申请号：US896929

申请日：1992-06-11

申请人： Hiroyuki Tsunoi ,  Kazumasa Nawata ,  Toshiaki Sakai ,  Hiroki Yada ,  Hisayosi Ooba ,  Takayuki Tsuru ,  Satoru Sudo ,  Taichi Saitoh

发明人： Hiroyuki Tsunoi ,  Kazumasa Nawata ,  Toshiaki Sakai ,  Hiroki Yada ,  Hisayosi Ooba ,  Takayuki Tsuru ,  Satoru Sudo ,  Taichi Saitoh

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/0136

摘要： A logic circuit in which first and second transistors are connected in series between high and low potential power sources with the middle point of the series connection used as the output terminal; A same- and inverse-phase signal generating unit is provided connected between the high and low potential power sources in parallel with the first and second transistors for generating same- and inverse-phase signals based on the single input signal output from the logic circuit. A transient signal generating unit is provided for generating transient large current signals at the rise time of the inverse-phase signals and generating transient cut-off signals at the fall time of the inverse-phase signals. The series connected first transistor is driven and controlled based on the regular-phase signals, while the second transistor is driven and controlled based on the transient large current signal and transient cut-off signal, thus producing an inverse-phase output by a simple circuit construction.

摘要翻译： 一种逻辑电路，其中第一和第二晶体管串联连接在高电平和低电位电源之间，串联中点用作输出端; 提供相同和反相信号产生单元，其连接在与第一和第二晶体管并联的高电平和低电位电源之间，用于基于从逻辑电路输出的单个输入信号产生相位和反相信号。 提供了一个瞬态信号发生单元，用于在反相信号的上升时间产生瞬时大电流信号，并在反相信号的下降时间产生瞬态截止信号。 基于正相信号驱动和控制串联的第一晶体管，而基于瞬态大电流信号和瞬态截止信号驱动和控制第二晶体管，从而通过简单电路产生反相输出 施工。