公开(公告)号：US4599521A

公开(公告)日：1986-07-08

申请号：US453113

申请日：1982-12-27

申请人： Yasunori Kanai ,  Eiji Sugiyama ,  Kazumasa Nawata

发明人： Yasunori Kanai ,  Eiji Sugiyama ,  Kazumasa Nawata

IPC分类号： G05F3/22 ,  H03K19/086 ,  H03K19/003 ,  H03K19/092 ,  H03K19/098

CPC分类号： H03K19/086 ,  G05F3/22 ,  G05F3/227

摘要： A bias circuit for providing a reference voltage to an output circuit, for example, an ECL circuit in an LSI. The bias circuit is able to operate at a lower power supply voltage of about -2 V and includes a first transistor having an emitter which is connected to a power supply and a base and a collector commonly connected through an impedance circuit to ground. The bias circuit is also connected to the output circuit, whereby heat generation in the LSI is decreased.

摘要翻译： 用于向输出电路提供参考电压的偏置电路，例如LSI中的ECL电路。 偏置电路能够在约-2V的较低电源电压下工作，并且包括具有连接到电源的发射极的第一晶体管，以及通过阻抗电路共同连接到地的基极和集电极。 偏置电路也连接到输出电路，由此降低LSI中的发热。

公开(公告)号：US4866303A

公开(公告)日：1989-09-12

申请号：US676836

申请日：1984-11-30

申请人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu

发明人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu

IPC分类号： H03K19/003 ,  H03K19/086 ,  H03K19/173

CPC分类号： H03K19/00353 ,  H03K19/086 ,  H03K19/1735

摘要： An ECL gate array comprising a plurality of basic cells. Each basic cell has a pair of emitter-coupled transistors, and a load connected between the collectors of the transistors and a power supply line. In accordance with a circuit design information, the resistance value of the load can be selected for increasing a noise margin of the output logic levels without deteriorating the switching speed.

摘要翻译： 包括多个基本单元的ECL门阵列。 每个基本单元具有一对发射极耦合晶体管，以及连接在晶体管的集电极和电源线之间的负载。 根据电路设计信息，可以选择负载的电阻值，以增加输出逻辑电平的噪声容限，而不会降低开关速度。

公开(公告)号：US5144158A

公开(公告)日：1992-09-01

申请号：US511958

申请日：1990-04-17

申请人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Hiroki Yada ,  Taichi Saitoh ,  Toshiaki Sakai

发明人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Hiroki Yada ,  Taichi Saitoh ,  Toshiaki Sakai

IPC分类号： H03K3/013 ,  H03K3/037

CPC分类号： H03K3/013 ,  H03K3/0375

摘要： A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.

摘要翻译： 包括至少三个门电路的锁存电路和一个噪声电阻电路。 第一门电路（3,4,11,16）接收数据信号（DT）和时钟信号（CLK）。 第二门电路（1,7,13,17）连接到第一门电路的输出端。 第三门电路（2,5,12,18）在输入端接收第一反相时钟信号（＆amp; upbar＆C）。 第三门电路的第二输入端连接到第二门电路的输出，并且第一输出端连接到第二门电路的输入端，从而在第二和第三门之间形成反馈线 电路。 噪声电阻电路（8,9,20,21）在反馈线中至少具有信号延迟元件。 噪声电阻电路可以包括滤波电路。 噪声电阻电路还可以包括放大器电路。

公开(公告)号：US4918563A

公开(公告)日：1990-04-17

申请号：US316532

申请日：1989-02-27

申请人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Toshiaki Sakai

发明人： Yasunori Kanai ,  Kazumasa Nawata ,  Mitsuhisa Shimizu ,  Toshiaki Sakai

IPC分类号： H03K19/086 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L29/00 ,  H03K19/003 ,  H03K19/173

CPC分类号： H03K19/00307 ,  H01L24/06 ,  H01L27/0248 ,  H01L27/11898 ,  H01L2224/05554

摘要： A semiconductor device such as an ECL gate array having emitter-follower-type output transistors, wherein protective elements are arranged between input/output pads and a power supply line connected to the collectors of the emitter-follower-type output transistors, whereby wiring between the protective elements and the power supply line become unnecessary so that the manufacturing process becomes easy and the integration degree is improved while a large tolerance voltage is maintained against destruction due to static electricity.

摘要翻译： 诸如具有发射极跟随器型输出晶体管的ECL门阵列的半导体器件，其中保护元件布置在输入/输出焊盘和连接到发射极跟随器型输出晶体管的集电极之间的电源线，由此在 保护元件和电源线变得不必要，使得制造过程变得容易，并且在保持大的公差电压以防止静电破坏的同时提高集成度。

公开(公告)号：US4678935A

公开(公告)日：1987-07-07

申请号：US650527

申请日：1984-09-14

申请人： Kazumasa Nawata ,  Yasunori Kanai

发明人： Kazumasa Nawata ,  Yasunori Kanai

IPC分类号： H01L21/822 ,  G05F3/22 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H03K19/00 ,  H03K19/086

CPC分类号： G05F3/22 ,  H03K19/086

摘要： An integrated circuit device having a simplified bias supply circuit for supplying bias power sources for a plurality of circuit units or cell units. The integrated circuit device cmprises: a cell unit array having a plurality of cell units disposed in a central portion of a semiconductor chip; a first power supply line and a second power supply line; and one or more common bias generating portions disposed at the periphery of the cell unit array, each of the common bias generating portions generating a single common bias voltage which differs from the potential of the second power supply line by a constant value. Each of the cell units comprises one or more logic circuit cells such as ECL type logic circuits, and an inner bias circuit which receives the common bias voltage and which generates a first inner bias voltage and a second inner bias voltage that are supplied to the respective logic circuit cell. The second inner bias voltage differs from the common bias voltage by a constant value, and the first inner bias voltage differs from the potential of the first power supply line at the cell unit by the value determined by the values of the elements in the inner bias circuit and by the common bias voltage.

摘要翻译： 一种具有用于为多个电路单元或单元单元提供偏置电源的简化偏置电源电路的集成电路装置。 集成电路装置包括：具有设置在半导体芯片的中心部分的多个单元单元的单元阵列阵列; 第一电源线和第二电源线; 以及设置在单元阵列阵列周边的一个或多个公共偏置产生部分，每个公共偏置产生部分产生与第二电源线的电位不同的单个公共偏置电压恒定值。 每个单元单元包括一个或多个逻辑电路单元，例如ECL型逻辑电路，以及内部偏置电路，其接收公共偏置电压，并产生提供给相应的第一内部偏置电压和第二内部偏置电压 逻辑电路单元。 第二内部偏置电压与公共偏置电压不同，并且第一内部偏置电压不同于单元单元处的第一电源线的电位由内部偏置中的元件的值确定的值 电路和公共偏置电压。

公开(公告)号：US20110261385A1

公开(公告)日：2011-10-27

申请号：US13177349

申请日：2011-07-06

申请人： Yasunori Kanai

发明人： Yasunori Kanai

IPC分类号： G06K15/02

CPC分类号： G06F3/1268 ,  G06F3/1204 ,  G06F3/1208 ,  G06F3/1258 ,  G06F3/1267 ,  G06F3/1285 ,  H04N1/00395 ,  H04N1/32561

摘要： A job processing method in a printing system having a printing apparatus which can accept a plurality of kinds of print jobs, wherein a print stop request of a print job which is to be printed by the printing apparatus is enabled by a user via a user interface section; and if a print job which is an object of a print stop is a print job which requires printing for a plurality of copies, the print stop processing of the print job is enabled by the printing apparatus in the print stop processing method based on a request from a user inputted via said user interface section in a plurality of kinds of print stop processing methods which can be executed in the printing apparatus.

摘要翻译： 一种打印系统中的作业处理方法，具有能够接受多种打印作业的打印装置，其中由打印装置打印的打印作业的打印停止请求由用户经由用户界面 部分; 并且如果作为打印停止的对象的打印作业是需要打印多个副本的打印作业，则通过打印装置在打印停止处理方法中基于请求使打印作业的打印停止处理能够被执行 从可以在打印装置中执行的多种打印停止处理方法经由所述用户界面部分输入的用户。

公开(公告)号：US5924024A

公开(公告)日：1999-07-13

申请号：US855416

申请日：1997-05-13

申请人： Yuka Ikeda ,  Yasunori Kanai

发明人： Yuka Ikeda ,  Yasunori Kanai

IPC分类号： H03D7/00 ,  H03C3/40 ,  H03D7/16 ,  H03D7/18 ,  H04B1/04 ,  H04B1/26 ,  H04B1/30 ,  H04Q9/12

CPC分类号： H04B1/30 ,  H03C3/40 ,  H03D7/165 ,  H04B2001/0491

摘要： A frequency conversion method and a frequency conversion circuit which enlarge the frequency difference between the upper and lower sidebands of the output signal so as to enable the undesired sideband to be easily eliminated by a filter even in a case where the frequency of the input signal is low. First, a first excitation signal having a first excitation frequency (Fp) is modulated by an input signal (a) of a predetermined frequency (F1) to produce two sidebands and thereby generate a first intermediate signal (b). Next, a second excitation signal having a second excitation frequency (Fq) lower than the first excitation frequency (Fp) by exactly a frequency twice the frequency of the input signal (a) is modulated by the input signal (a) to produce two sidebands and thereby generate a second intermediate signal (c). Further the first intermediate signal (b) and the second intermediate signal (c) are added so that the lower sideband of the first intermediate signal (b) and the upper sideband of the second intermediate signal (c) are cancelled by each other to thereby generate an output signal (d) composed of the upper sideband of the first intermediate signal (b) and the lower sideband of the second intermediate signal (c). By this, the space between the upper sideband and the lower sideband is widened and thereby the lower band erasing filter can easily erase the lower sideband.

摘要翻译： 一种频率转换方法和频率转换电路，其扩大了输出信号的上边带和下边带之间的频差，使得即使在输入信号的频率为 低。 首先，具有第一激励频率（Fp）的第一激励信号由预定频率（F1）的输入信号（a）调制以产生两个边带，从而产生第一中间信号（b）。 接下来，通过输入信号（a）调制具有低于第一激励频率（Fp）的第二激励频率（Fq）的精度为输入信号（a）的两倍的频率的第二激励信号，以产生两个边带 从而产生第二中间信号（c）。 此外，第一中间信号（b）和第二中间信号（c）相加，使得第一中间信号（b）的下边带和第二中间信号（c）的上边带彼此抵消，从而 产生由第一中间信号（b）的上边带和第二中间信号（c）的下边带组成的输出信号（d）。 由此，上边带和下边带之间的空间被加宽，从而下带消除滤波器可以容易地擦除下边带。

公开(公告)号：US4530002A

公开(公告)日：1985-07-16

申请号：US391161

申请日：1982-06-22

申请人： Yasunori Kanai

发明人： Yasunori Kanai

IPC分类号： H05K1/18 ,  H01L23/055 ,  H01L23/057 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H05K3/34 ,  H01L23/48

CPC分类号： H05K3/3415 ,  H01L23/055 ,  H01L23/057 ,  H01L23/49827 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/30107 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K3/3421 ,  H05K3/3447 ,  Y02P70/613

摘要： A semiconductor device having improved construction of connection leads extending from the chip carrier housing for connecting a semiconductor chip in the housing with the external circuitry. The connection leads are arranged in the form of a plurality of concentric arrays. The leads in the outermost array are composed of surface connection leads to be electrically connected to the uppermost layer of a multilayer printed board to which the semiconductor device will be mounted, and the leads in the inner array or arrays are composed of lead pins to be inserted into and be electrically connected to the through holes of the multilayer printed board.

摘要翻译： 一种半导体器件，其具有从芯片载体壳体延伸的连接引线的改进结构，用于将壳体中的半导体芯片与外部电路连接。 连接引线以多个同心圆盘的形式布置。 最外面阵列中的引线由表面连接引线组成，电连接到多层印刷电路板的最上层，半导体器件将被安装到其上，内部阵列或阵列中的引线由引脚引脚组成 插入并电连接到多层印刷电路板的通孔。

公开(公告)号：US4410816A

公开(公告)日：1983-10-18

申请号：US327692

申请日：1981-12-04

申请人： Yasunori Kanai

发明人： Yasunori Kanai

IPC分类号： H03K19/00 ,  G01R31/316 ,  H01L21/33 ,  H01L21/331 ,  H01L21/66 ,  H01L29/70 ,  H01L29/73 ,  H03K19/003 ,  H03K19/086

CPC分类号： H03K19/00307 ,  G01R31/316 ,  H03K19/086

摘要： An ECL integrated circuit comprises an emitter-follower transistor at the output stage and a pull-down resistor connected to the emitter-follower transistor. The ECL integrated circuit is provided with a test circuit on a line extending from the output of emitter-follower transistor to a subsequent stage so as to cause a test current to flow only at the time of the test. The test current is smaller than the current usually flowing to the pull-down resistor but larger than the current flowing to the subsequent stage.

摘要翻译： ECL集成电路包括在输出级的发射极跟随器晶体管和连接到发射极跟随器晶体管的下拉电阻。 ECL集成电路在从发射极跟随器晶体管的输出延伸到后续级的线上设置有测试电路，以便仅在测试时使测试电流流动。 测试电流小于通常流向下拉电阻的电流，但大于流向后续级的电流。

公开(公告)号：US08493603B2

公开(公告)日：2013-07-23

申请号：US13177349

申请日：2011-07-06

申请人： Yasunori Kanai

发明人： Yasunori Kanai

IPC分类号： G06F3/12 ,  G06K15/00

CPC分类号： G06F3/1268 ,  G06F3/1204 ,  G06F3/1208 ,  G06F3/1258 ,  G06F3/1267 ,  G06F3/1285 ,  H04N1/00395 ,  H04N1/32561

摘要： A job processing method in a printing system having a printing apparatus which can accept a plurality of kinds of print jobs, wherein a print stop request of a print job which is to be printed by the printing apparatus is enabled by a user via a user interface section; and if a print job which is an object of a print stop is a print job which requires printing for a plurality of copies, the print stop processing of the print job is enabled by the printing apparatus in the print stop processing method based on a request from a user inputted via said user interface section in a plurality of kinds of print stop processing methods which can be executed in the printing apparatus.

摘要翻译： 一种打印系统中的作业处理方法，具有能够接受多种打印作业的打印装置，其中由打印装置打印的打印作业的打印停止请求由用户经由用户界面 部分; 并且如果作为打印停止的对象的打印作业是需要打印多个副本的打印作业，则通过打印装置在打印停止处理方法中基于请求使打印作业的打印停止处理能够被执行 从可以在打印装置中执行的多种打印停止处理方法经由所述用户界面部分输入的用户。