-
1.发明授权System and method for metal residue detection and mapping within a multi-step sequence 失效多步序列中金属残留检测和映射的系统和方法公开(公告)号：US06929531B2
公开(公告)日：2005-08-16
申请号：US10251033
申请日：2002-09-19
CPC分类号： B24B37/042 , B24B49/02 , B24B49/10 , H01L21/3212 , H01L22/00
摘要： A system and method of measuring a metallic layer on a substrate within a multi-step substrate process includes modifying a metallic layer on the substrate such as forming a metallic layer or removing at least a portion of the metallic layer. At least one sensor is positioned a predetermined distance from the surface of the substrate. The surface of the substrate is mapped to determine a uniformity of the metallic layer on the surface of the substrate.
摘要翻译： 在多步衬底工艺中测量衬底上的金属层的系统和方法包括改变衬底上的金属层，例如形成金属层或去除金属层的至少一部分。 至少一个传感器定位在离基板表面预定距离处。 映射衬底的表面以确定衬底表面上的金属层的均匀性。
-
公开(公告)号：US20050000653A1
公开(公告)日：2005-01-06
申请号：US10881094
申请日：2004-06-29
IPC分类号： C23F1/00 , G01B7/06 , G01R27/00 , H01L21/302
CPC分类号： G01B7/105 , G01B7/107 , G01B2210/44
摘要： A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A sensor array external to the CMP tool is included. The sensor array is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The sensor array provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.
-
3.发明申请Method and apparatus for wafer mechanical stress monitoring and wafer thermal stress monitoring 审中-公开用于晶片机械应力监测和晶片热应力监测的方法和装置公开(公告)号：US20050066739A1
公开(公告)日：2005-03-31
申请号：US10671978
申请日：2003-09-26
CPC分类号： B24B37/015 , B24B49/16
摘要： A chemical mechanical planarization (CMP) system is provided. The CMP system includes a wafer carrier configured to support a wafer during a planarization process, the wafer carrier including a sensor configured to detect a signal indicating a stress being experienced by the wafer during planarization. A computing device in communication with the sensor is included. The computing device is configured to translate the signal to generate a stress map for analysis. A stress relief device responsive to a signal received from the computing device is included. The stress relief device is configured to relieve the stress being experienced by the wafer.
摘要翻译： 提供化学机械平面化（CMP）系统。 CMP系统包括被配置为在平坦化处理期间支撑晶片的晶片载体，晶片载体包括被配置成在平坦化期间检测指示由晶片经历的应力的信号的传感器。 包括与传感器通信的计算设备。 计算设备被配置为平移信号以产生用于分析的应力图。 包括响应于从计算设备接收的信号的应力消除装置。 应力释放装置被构造成减轻晶片经历的应力。
-
4.发明申请公开(公告)号：US20050007107A1
公开(公告)日：2005-01-13
申请号：US10914017
申请日：2004-08-05
CPC分类号： H01L22/26
摘要： A method for detecting a thickness of a layer of a wafer to be processed is provided. The method includes defining a plurality of sensors configured to create a set of complementary sensors proximate the wafer. Further included in the method is distributing the plurality of sensors along a particular radius of the wafer such that each sensor of the plurality of sensors is out of phase with an adjacent sensor by a same angle. The method also includes measuring signals generated by the plurality of sensors. Further included is averaging the signals generated by the plurality of sensors so as to generate a combination signal. The averaging is configured to remove noise from the combination signal such that the combination signal is capable of being correlated to identify the thickness of the layer.
摘要翻译： 提供了一种用于检测待处理晶片层的厚度的方法。 该方法包括限定配置成在晶片附近产生一组互补传感器的多个传感器。 该方法中还包括沿着晶片的特定半径分布多个传感器，使得多个传感器中的每个传感器与相邻的传感器相异相同角度。 该方法还包括测量由多个传感器产生的信号。 还包括对由多个传感器产生的信号进行平均以产生组合信号。 平均化被配置为从组合信号去除噪声，使得组合信号能够被相关联以识别层的厚度。
-
5.发明申请Method and apparatus for slope to threshold conversion for process state monitoring and endpoint detection 有权用于过程状态监测和端点检测的斜率到阈值转换的方法和装置公开(公告)号：US20050125202A1
公开(公告)日：2005-06-09
申请号：US11030374
申请日：2005-01-05
申请人： Yehiel Gotkis , Vladimir Katz , David Hemker , Rodney Kistler , Nicolas Bright
发明人： Yehiel Gotkis , Vladimir Katz , David Hemker , Rodney Kistler , Nicolas Bright
CPC分类号： G05B23/0254 , H01L22/26
摘要： A method for converting a slope based detection task to a threshold based detection task is provided. The method initiates with defining an approximation equation for a set of points corresponding to values of a process being monitored. Then, an expected value at a current point of the process being monitored is predicted. Next, a difference between a measured value at the current point of the process being monitored and the corresponding expected value is calculated. Then, the difference is monitored for successive points to detect a deviation value between the measured value and the expected value. Next, a transition point for the process being monitored is identified based on the detection of the deviation value. A processing system configured to provide real time data for a slope based transition and a computer readable media are also provided.
摘要翻译： 提供了一种将基于斜率的检测任务转换为基于阈值的检测任务的方法。 该方法通过为对应于被监视的进程的值的一组点定义近似方程来启动。 然后，预测在被监视的处理的当前点的期望值。 接下来，计算被监视处理当前点的测量值与对应的期望值之间的差值。 然后，对连续点监测差异，以检测测量值和预期值之间的偏差值。 接下来，基于偏差值的检测来识别被监视处理的转变点。 还提供了一种处理系统，其被配置为提供用于基于斜率的转换的实时数据和计算机可读介质。
-
6.发明申请Process integration scheme to lower overall dielectric constant in BEoL interconnect structures 有权过程集成方案，以降低BEoL互连结构中的总体介电常数公开(公告)号：US20080150138A1
公开(公告)日：2008-06-26
申请号：US11732198
申请日：2007-04-02
申请人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
发明人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
IPC分类号： H01L21/4763 , H01L23/52
CPC分类号： H01L21/76822 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
摘要翻译： 提供了后端（BEoL）互连结构及其制造方法。 这些结构的特征在于导线越窄，总介电常数值越小。 保形扩散阻挡层和选择性形成的覆盖层用于将导线和通孔与互连结构中的周围电介质层隔离。 本发明的方法采用技术来缩小光致抗蚀剂掩模中的开口，以便限定更窄的通孔。 更窄的通孔增加了通孔和导电线之间可以容许的不对准量。
-
7.发明申请PROCESS INTEGRATION SCHEME TO LOWER OVERALL DIELECTRIC CONSTANT IN BEOL INTERCONNECT STRUCTURES 审中-公开过程集成方案降低BEOL互连结构中的总体电介质常数公开(公告)号：US20090134520A1
公开(公告)日：2009-05-28
申请号：US12366235
申请日：2009-02-05
申请人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
发明人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
IPC分类号： H01L23/52
CPC分类号： H01L21/76822 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
摘要翻译： 提供了后端（BEoL）互连结构及其制造方法。 这些结构的特征在于导线越窄，总体介电常数值越小。 保形扩散阻挡层和选择性形成的覆盖层用于将导线和通孔与互连结构中的周围电介质层隔离。 本发明的方法采用技术来缩小光致抗蚀剂掩模中的开口，以便限定更窄的通孔。 更窄的通孔增加了通孔和导电线之间可以容许的不对准量。
-
8.发明授权公开(公告)号：US09076844B2
公开(公告)日：2015-07-07
申请号：US12366235
申请日：2009-02-05
申请人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
发明人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
IPC分类号： H01L23/52 , H01L29/40 , H01L21/768
CPC分类号： H01L21/76822 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
-
公开(公告)号：US07899627B2
公开(公告)日：2011-03-01
申请号：US11536577
申请日：2006-09-28
申请人： Chung-Ho Huang , Jackie Seto , Nicolas Bright
发明人： Chung-Ho Huang , Jackie Seto , Nicolas Bright
CPC分类号： H01J37/3299 , H01J37/32935
摘要： In a plasma processing system, a method for dynamically establishing a baseline is provided. The method includes processing a first substrate. The method also includes collecting a first signal data for the first substrate. The method further includes comparing the first signal data against the baseline. The method moreover includes including the first signal data in a recalculation of the baseline if the first signal data is within a confidence level range, which is in between a top level above the baseline and a bottom level below the baseline.
摘要翻译： 在等离子体处理系统中，提供了用于动态建立基线的方法。 该方法包括处理第一衬底。 该方法还包括收集第一基底的第一信号数据。 该方法还包括将第一信号数据与基线进行比较。 该方法还包括如果第一信号数据在置信水平范围内的第一信号数据重新计算基线，其置于高于基线的最高水平和低于基线的底部水平之间。
-
公开(公告)号：US07465525B2
公开(公告)日：2008-12-16
申请号：US11126466
申请日：2005-05-10
申请人： S. M. Reza Sadjadi , Nicolas Bright
发明人： S. M. Reza Sadjadi , Nicolas Bright
IPC分类号： G03F9/00
CPC分类号： H01L21/0338 , G03F7/70433 , G03F7/70466
摘要： A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.
摘要翻译： 提供了一种用于产生多个标线布局的方法。 接收具有特征布局间距的特征布局。 从特征布局生成多个标线布局，其中多个标线布局的每个标线布局具有标线布局间距，并且其中每个标线布局间距至少是特征布局间距的两倍。
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.021 秒)
