公开(公告)号：US06228713B1

公开(公告)日：2001-05-08

申请号：US09342035

申请日：1999-06-28

申请人： Yelehanka Ramachandramurthy Pradeep ,  Vijay Kumar Chhagan ,  Jie Yu ,  Mei Sheng Zhou

发明人： Yelehanka Ramachandramurthy Pradeep ,  Vijay Kumar Chhagan ,  Jie Yu ,  Mei Sheng Zhou

IPC分类号： H01H21336

CPC分类号： H01L27/11521 ,  H01L21/76224

摘要： A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.

摘要翻译： 一种在存储器件中制作自对准浮动栅极的方法。 该方法使用用于浅沟槽隔离（STI）的沟槽蚀刻对浮栅（FG）进行图案化。 因为浮动栅极（FG）与凸起的STI相邻，所以在FG和CG之间消除了尖角，从而增加了栅间电介质层的有效性。 该方法包括：在衬底上形成第一介质层（栅极氧化物）和多晶硅层，蚀刻通过第一电介质氧化物层和多晶硅层并进入衬底以形成沟槽。 剩余的第一电介质层和多晶硅层用作隧道电介质层和浮栅。 沟槽填充有隔离层。 去除掩模层。 在浮栅和隔离层上形成隔间电介质层和控制栅极。

公开(公告)号：US6156598A

公开(公告)日：2000-12-05

申请号：US460113

申请日：1999-12-13

申请人： Mei Sheng Zhou ,  Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Ying Keung Leung

发明人： Mei Sheng Zhou ,  Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Ying Keung Leung

IPC分类号： H01L21/265 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66598 ,  H01L21/2652 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659

摘要： A method for forming an L-shaped spacer using a sacrificial organic top coating, then using the L-shaped spacer to simultaneously implant lightly doped source and drain extensions through the L-shaped spacer while implanting source and drain regions beyond the L-shaped spacer. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiments, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer. Impurity ions are implanted into the surface of the semiconductor structure forming lightly doped source and drain extensions where the ions are implanted through the L-shaped spacer, and forming source and drain regions beyond the L-shaped spacer where the ions are implanted without passing through the L-shaped spacer.

摘要翻译： 使用牺牲有机顶涂层形成L形间隔物的方法，然后使用L形间隔物同时将轻掺杂的源极和漏极延伸部注入L型间隔物，同时将源极和漏极区域注入超过L形间隔物 。 提供其上具有栅极结构的半导体结构。 在栅极结构上形成衬里氧化物层。 介电间隔层形成在衬垫氧化物层上。 在优选实施例中，电介质间隔层包括氮化硅层或氮氧化硅层。 在电介质间隔层上形成牺牲有机层。 牺牲有机层和电介质间隔层被各向异性蚀刻以形成包括三角形牺牲有机结构和L形介电间隔物的间隔物。 去除三角形牺牲有机结构留下L形介电隔离物。 将杂质离子注入到形成轻掺杂源极和漏极延伸部分的半导体结构的表面中，其中离子通过L形间隔物注入，并且形成超过L形间隔物的源极和漏极区域，其中离子被注入而不通过 L形间隔物。

公开(公告)号：US5858847A

公开(公告)日：1999-01-12

申请号：US827239

申请日：1997-03-28

申请人： Mei Sheng Zhou ,  Yelehanka Ramachandramurthy Pradeep ,  Dajiang Xu

发明人： Mei Sheng Zhou ,  Yelehanka Ramachandramurthy Pradeep ,  Dajiang Xu

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/47

CPC分类号： H01L29/6659 ,  H01L21/0331 ,  H01L21/266 ,  H01L21/8238

摘要： The present invention provides a method of manufacturing a lightly doped drain (LDD) structure using a polymer layer to define the LDD. The polymer layer is formed in an etch step which defines the gate electrode. The method begins by forming spaced field oxide regions 12 in a substrate 10. Next, a gate oxide layer 14, and a material layer 18 and a hard mask layer 22 are sequentially formed over the active area and the field oxide regions 12. A photo resist block 24 is formed over the hard mask layer 22 over the active area. The hard mask layer 22 is etched using the photo resist block 24 as a mask forming a hard mask block 22. The etch simultaneously forms a polymer layer 26 over the a top and sidewalls of the photo resist block 24 and over the sidewalls of the hard mask block. Impurities ions are implanted into the substrate in the active area using the polymer layer 26 as a mask forming highly doped drain regions 30 in the substrate 10. Next, the photo resist block 24 and the polymer layer 26 are removed. The hard mask is used as an etch barrier to etch the gate material to form a gate electrode 19 between the lightly doped drains. Subsequently, impurities ions are implanted into the substrate in the active area using the hard mask block 23 as a mask forming lightly doped drain regions 34 in the substrate 10.

摘要翻译： 本发明提供一种使用聚合物层制造用于限定LDD的轻掺杂漏极（LDD）结构的方法。 聚合物层在限定栅电极的蚀刻步骤中形成。 该方法通过在衬底10中形成间隔的场氧化物区域12开始。接下来，栅极氧化物层14以及材料层18和硬掩模层22依次形成在有源区域和场氧化物区域12上。照片 抗蚀剂块24形成在有源区域上方的硬掩模层22上。 使用光致抗蚀剂块24作为形成硬掩模块22的掩模来蚀刻硬掩模层22.蚀刻同时在光致抗蚀剂块24的顶部和侧壁上以及硬质掩模22的侧壁之上形成聚合物层26。 掩模块。 使用聚合物层26作为在衬底10中形成高度掺杂的漏极区域30的掩模将杂质离子注入到有源区域中的衬底中。接下来，除去光致抗蚀剂块24和聚合物层26。 硬掩模用作蚀刻栅极以蚀刻栅极材料以在轻掺杂漏极之间形成栅电极19。 随后，使用硬掩模块23作为形成衬底10中的轻掺杂漏区34的掩模，在有源区中将杂质离子注入到衬底中。

公开(公告)号：US06303447B1

公开(公告)日：2001-10-16

申请号：US09502036

申请日：2000-02-11

申请人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

发明人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中所述沟槽的宽度大于所述栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

公开(公告)号：US06387765B2

公开(公告)日：2002-05-14

申请号：US09946982

申请日：2001-09-06

申请人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

发明人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; therein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中沟槽的宽度大于栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

公开(公告)号：US5866448A

公开(公告)日：1999-02-02

申请号：US902757

申请日：1997-07-30

申请人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

发明人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  Y10S438/963

摘要： A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall. After removal of the polymer and residual photoresist, the source/drain implant is performed, followed by removal of the polysilicon lip by RIE using the cap oxide as a mask. The LDD implant is then performed.

摘要翻译： 描述了一种制造用于自对准多晶硅栅极MOSFET的轻掺杂漏极（LDD）结构的方法，其中在多晶硅栅电极的图案化工艺期间沿侧壁形成的聚合物层用于掩蔽源/漏 离子植入。 侧壁聚合物层代替常规的氧化硅侧壁作为LDD间隔物，并提供改进的厚度控制以及改进的处理步骤顺序，从而消除间隔氧化物层沉积到栅极氧化物上。 首先沉积在栅极多晶硅层上的覆盖氧化物层。 然后使用RIE在沿着氧化物图案的边缘形成聚合物侧壁层的条件下对该氧化物层进行构图和蚀刻。 然后蚀刻多晶硅层，并且具有与盖氧化物图案同心的图案，但是通过聚合物侧壁的厚度更宽。 在去除聚合物和残余光致抗蚀剂之后，进行源极/漏极注入，随后通过RIE使用帽氧化物作为掩模去除多晶硅唇缘。 然后执行LDD植入。

公开(公告)号：US08394724B2

公开(公告)日：2013-03-12

申请号：US11843629

申请日：2007-08-22

申请人： Hai Cong ,  Wei Loong Loh ,  Krishan Gopal ,  Xin Zhang ,  Mei Sheng Zhou ,  Pradeep Ramachandramurthy Yelehanka

发明人： Hai Cong ,  Wei Loong Loh ,  Krishan Gopal ,  Xin Zhang ,  Mei Sheng Zhou ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L21/312

CPC分类号： H01L21/32137 ,  H01L21/32139

摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

摘要翻译： 用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

公开(公告)号：US08324011B2

公开(公告)日：2012-12-04

申请号：US11853156

申请日：2007-09-11

申请人： Chyiu Hyia Poon ,  Alex See ,  Mei Sheng Zhou

发明人： Chyiu Hyia Poon ,  Alex See ,  Mei Sheng Zhou

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/268

摘要： The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

摘要翻译： 本发明提供了一种通过向半导体结构施加温度相关的相位开关层来退火半导体的方法。 温度相关的相位开关层在预定温度下将相从非晶形变化为结晶。 当半导体结构退火时，电磁辐射在到达半导体结构之前通过温度相关的相位开关层。 当达到期望的退火温度时，温度相关的相位开关层基本上阻止电磁辐射到达半导体结构。 结果，半导体在晶片上以一致的温度退火。 温度相关的相位开关层改变相位的温度可以通过离子注入工艺来控制。

公开(公告)号：US20110281410A1

公开(公告)日：2011-11-17

申请号：US13190805

申请日：2011-07-26

申请人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US08012839B2

公开(公告)日：2011-09-06

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。