公开(公告)号：US06303447B1

公开(公告)日：2001-10-16

申请号：US09502036

申请日：2000-02-11

申请人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

发明人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中所述沟槽的宽度大于所述栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

公开(公告)号：US06387765B2

公开(公告)日：2002-05-14

申请号：US09946982

申请日：2001-09-06

申请人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

发明人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; therein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中沟槽的宽度大于栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

公开(公告)号：US06211008B1

公开(公告)日：2001-04-03

申请号：US09528241

申请日：2000-03-17

申请人： Jie Yu ,  Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jun Qian

发明人： Jie Yu ,  Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jun Qian

IPC分类号： H01L218242

CPC分类号： H01L28/91

摘要： A method for fabricating a high-density high-capacity capacitor is described. A dielectric layer is provided overlying a semiconductor substrate. A sacrificial layer is deposited overlying the dielectric layer and patterned to form a pattern having a large surface area within a small area on the substrate. In one alternative, spacers are formed on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. A bottom capacitor plate layer is conformally deposited overlying the spacers. In a second alternative, a bottom capacitor plate layer is deposited overlying the patterned sacrificial layer and etched to leave spacers on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. In both alternatives, a capacitor dielectric layer is deposited overlying the bottom capacitor plate layer. A top capacitor plate layer is deposited overlying the capacitor dielectric layer and patterned to complete fabrication of a high-density high-capacity capacitor.

摘要翻译： 对高密度大容量电容器的制造方法进行说明。 提供覆盖在半导体衬底上的电介质层。 牺牲层沉积在电介质层上并被图案化以形成在衬底上的小区域内具有大表面积的图案。 在一个替代方案中，间隔物形成在图案化牺牲层的侧壁上。 此后，除去牺牲层。 底部电容器平板层被共形地沉积在隔离物上。 在第二替代方案中，沉积底部电容器板层，覆盖图案化的牺牲层并被蚀刻以在图案化牺牲层的侧壁上留下间隔物。 此后，除去牺牲层。 在两种替代方案中，电容器电介质层沉积在底部电容器板层上。 沉积在电容器电介质层上的顶部电容器平板层被图案化以完成高密度大容量电容器的制造。

公开(公告)号：US06281093B1

公开(公告)日：2001-08-28

申请号：US09619016

申请日：2000-07-19

申请人： Yelehanka Ramachandramurthy Pradeep ,  Qinghua Zhong ,  Zheng Zou ,  Henry Gerung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Qinghua Zhong ,  Zheng Zou ,  Henry Gerung

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/76224

摘要： A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

摘要翻译： 已经实现了制造浅沟槽隔离的新方法。 在半导体衬底上形成二氧化硅层。 沉积氮化硅层覆盖二氧化硅层。 图案化氮化硅层以暴露其中规划浅沟槽隔离的半导体衬底。 将离子注入到暴露的半导体衬底中。 植入损伤覆盖半导体衬底的任何被动表面材料。 暴露的半导体衬底被蚀刻以形成沟槽。 在蚀刻期间，损坏的被动表面材料被去除，从而防止形成沟槽。 沉积沟槽填充层以填充沟槽。 在集成电路器件的制造中，沟槽填充层被抛光以完成浅沟槽隔离。

公开(公告)号：US06228770B1

公开(公告)日：2001-05-08

申请号：US09531784

申请日：2000-03-21

申请人： Yelehanka Ramachandramurthy Pradeep ,  Vijai Kumar Chhagan ,  Henry Gerung ,  Madhusudan Mukhopadhyay

发明人： Yelehanka Ramachandramurthy Pradeep ,  Vijai Kumar Chhagan ,  Henry Gerung ,  Madhusudan Mukhopadhyay

IPC分类号： H01L2100

CPC分类号： H01L21/7682

摘要： A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer. The self-sealing oxide layer seals over the gaps between the silicon nitride thin layer and the silicon nitride liner layer to thereby form permanent air gaps between the adjacent metal interconnects, and the integrated circuit is completed.

摘要翻译： 实现了在制造集成电路器件中在相邻互连之间形成具有气隙的金属互连的新方法。 提供半导体衬底。 金属互连形成在半导体衬底上。 沉积氮化硅衬垫层。 沉积间隙填充氧化物层以填充相邻的金属互连之间的间隙。 间隙填充氧化物层被抛光到氮化硅衬垫层。 沉积氮化硅薄层。 使用金属互连的过大的反向掩模来对氮化硅薄层进行构图。 氮化硅薄层的图案化形成开口，从而暴露间隙填充氧化物的一部分。 间隙填充氧化物层被蚀刻掉。 沉积氮化硅薄层和氮化硅衬层的自密封氧化层。 自密封氧化物层在氮化硅薄层和氮化硅衬垫层之间的间隙上密封，从而在相邻的金属互连之间形成永久的气隙，并且完成集成电路。

公开(公告)号：US06337262B1

公开(公告)日：2002-01-08

申请号：US09519611

申请日：2000-03-06

申请人： Yelehanka Ramachandramurthy Pradeep ,  Chivukula Subrahmanyam ,  Vijai Kumar Chhagan ,  Henry Gerung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Chivukula Subrahmanyam ,  Vijai Kumar Chhagan ,  Henry Gerung

IPC分类号： H01L2128

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L29/66553

摘要： A new method is provided for the integration of the of T-top gate process. Active regions are defined and bounded by STI's on the surface of a substrate. The pad oxide is removed from the substrate and replaced by a layer of SAC oxide. A thin layer of nitride is deposited that covers the surface of the created layer of SAC oxide and the surface of the STI regions. A layer of TEOS is deposited and etched defining the regions where the gate electrodes need to be formed. Gate spacers are next formed on the sidewalls of the openings that have been created in the layer of TEOS. The required implants (such as channel implant and threshold implant) are performed, the gate structure is then grown in the openings that have been created in the layer of TEOS. After the gate structure has been completed, the surface of the created structure is polished and the remaining layer of TEOS is removed. Source and drain regions implants can now be performed, LDD regions are implanted using a tilted implant. This tilted implant penetrates underneath the body of the created gate structures thereby creating the LDD regions. The removal of the layer of TEOS leaves in place the gate structures, one such structure is located in the active region of the surface of the substrate, two additional structures that have been created on the surface of the STI regions.

摘要翻译： 提供了一种用于集成T-top门过程的新方法。 有源区域由衬底表面上的STI限定和界定。 衬垫氧化物从衬底上去除并被一层SAC氧化物代替。 沉积薄层的氮化物，其覆盖所形成的SAC氧化物层的表面和STI区域的表面。 沉积和蚀刻一层TEOS，限定需要形成栅电极的区域。 接下来，在已经在TEOS层中形成的开口的侧壁上形成栅极间隔物。 执行所需的植入物（例如通道植入和阈值植入），然后在已经在TEOS层中产生的开口中生长栅极结构。 在栅极结构完成之后，对所形成的结构的表面进行抛光并除去TEOS的剩余层。 现在可以执行源极和漏极区域植入，使用倾斜植入物植入LDD区域。 这种倾斜的植入物渗透在所产生的栅极结构的主体下面，从而形成LDD区域。 TEOS层的去除留下了栅极结构，一个这样的结构位于衬底的表面的有源区域中，在STI区域的表面上产生了两个另外的结构。

公开(公告)号：US06300251B1

公开(公告)日：2001-10-09

申请号：US09501967

申请日：2000-02-10

申请人： Yelehanka Ramachandramurthy Pradeep ,  Vijakomar Chhagan ,  Henry Gerung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Vijakomar Chhagan ,  Henry Gerung

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for anisotropically etching a partially manufactured semiconductor structure, more specifically, a stacked FET gate structure containing a bottom anti-reflective coating (Barc) layer is described. The structure is covered with a photoresist layer which is patterned to defines the gate region. The processing chemistry is predominantly carbon tetrafluoride, (CF4) with the inclusion of chlorine (Cl2) where fluorine (F) is generated in the plasma as the etchant for the structure. During processing, the wafer is cooled with helium (He) that lowers the wafer temperature and promotes sidewall deposition from the fluorine species which acts as a passivation layer producing a anisotropic or vertical etch profile. The process reduces etch time and results in very repeatable end point control of the Bark etch and poly cap etch improving the control of the structure critical dimensions and improving process throughput. The reduction in the use of fluorine based species reduces any potential environmental impact.

摘要翻译： 描述了用于各向异性蚀刻部分制造的半导体结构的方法，更具体地，描述了包含底部抗反射涂层（Barc）层的层叠FET栅极结构。 该结构被图案化以限定栅极区域的光致抗蚀剂层覆盖。 处理化学主要是四氟化碳（CF4），其包含氯（Cl2），其中在等离子体中产生氟（F）作为结构的蚀刻剂。 在处理过程中，用氦（氦）冷却晶片，从而降低晶片温度并促进作为钝化层的氟物质的侧壁沉积，产生各向异性或垂直蚀刻轮廓。 该方法减少蚀刻时间，并导致巴克蚀刻和聚盖蚀刻的非常可重复的终点控制，从而改善结构关键尺寸的控制并提高工艺流程。 氟类物质的使用减少减少了任何潜在的环境影响。

公开(公告)号：US06277683B1

公开(公告)日：2001-08-21

申请号：US09514900

申请日：2000-02-28

申请人： Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jie Yu ,  Pei Ching Lee

发明人： Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jie Yu ,  Pei Ching Lee

IPC分类号： H01L218238

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

摘要： A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900° C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.

摘要翻译： 在相同的半导体衬底上形成水化CMOS器件和非硅化物半导体器件的方法，其仅使用一个氮化硅层来提供用于复合间隔物的部件用于在水化CMOS器件的侧面，并提供阻挡形状 在金属硅化物形成期间，对于非水银CMOS器件，已经开发出来。 该方法的特征在于，对于所有CMOS器件，在多晶硅栅极结构的侧面上使用用于限定重掺杂源极/漏极区域的一次性有机间隔物。 然后在800至900℃的温度下通过LPCVD方法获得的氮化硅层被沉积和图案化以在经历自对准硅化物工艺的CMOS器件的侧面上提供所需的间隔物，而同一氮化硅层 用于提供防止非水银CMOS器件形成金属硅化所需的阻挡形状。

公开(公告)号：US06284637B1

公开(公告)日：2001-09-04

申请号：US09280023

申请日：1999-03-29

申请人： Vijai Komar N. Chhagan ,  Yelehanka Machandramurthy Pradee ,  Mei Sheng Zhou ,  Henry Gerung

发明人： Vijai Komar N. Chhagan ,  Yelehanka Machandramurthy Pradee ,  Mei Sheng Zhou ,  Henry Gerung

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L29/7883

摘要： A method to fabricate a floating gate with a sloping sidewall for a Flash Memory is described. Field oxide isolation regions are provided in the substrate. A silicon oxide layer is provided overlying the isolation regions and the substrate. A first polysilicon layer is deposited overlying the silicon oxide layer. A photoresist layer is deposited overlying the first polysilicon layer. The photoresist layer is etched to remove sections of the photoresist as defined by photolithographic process. The photoresist layer, the first polysilicon layer, and the silicon oxide layer are etched in areas uncovered by the photoresist layer to create structures with sloping sidewall edges. The photoresist layer is etched away. An interpoly dielectric layer is deposited overlying the structures, the sloping sidewall edges, and the isolation regions. A second polysilicon layer is deposited overlying the interpoly dielectric and the fabrication of the integrated circuit device is completed.

摘要翻译： 描述了一种用于制造具有用于闪存的倾斜侧壁的浮动栅极的方法。 在衬底中提供场氧化物隔离区。 提供覆盖隔离区域和衬底的氧化硅层。 沉积在氧化硅层上的第一多晶硅层。 沉积在第一多晶硅层上的光致抗蚀剂层。 蚀刻光致抗蚀剂层以除去由光刻工艺定义的光致抗蚀剂部分。 光刻胶层，第一多晶硅层和氧化硅层被蚀刻在未被光致抗蚀剂层覆盖的区域中，以产生具有倾斜侧壁边缘的结构。 蚀刻掉光致抗蚀剂层。 叠层介质层沉积在结构上，倾斜的侧壁边缘和隔离区域上。 第二多晶硅层沉积在叠层电介质上，并且完成了集成电路器件的制造。

公开(公告)号：US07591871B1

公开(公告)日：2009-09-22

申请号：US11060157

申请日：2005-02-17

申请人： Henry Gerung ,  Timothy J. Boyle ,  Scott D. Bunge

发明人： Henry Gerung ,  Timothy J. Boyle ,  Scott D. Bunge

IPC分类号： B22F9/24

CPC分类号： B22F9/24 ,  B22F2998/00 ,  B22F2999/00 ,  B22F1/0014 ,  B22F1/0018 ,  B22F1/0025 ,  B22F2203/11

摘要： A method for providing a route for the synthesis of a Ge(0) nanometer-sized material from. A Ge(II) precursor is dissolved in a ligand heated to a temperature, generally between approximately 100° C. and 400° C., sufficient to thermally reduce the Ge(II) to Ge(0), where the ligand is a compound that can bond to the surface of the germanium nanomaterials to subsequently prevent agglomeration of the nanomaterials. The ligand encapsulates the surface of the Ge(0) material to prevent agglomeration. The resulting solution is cooled for handling, with the cooling characteristics useful in controlling the size and size distribution of the Ge(0) materials. The characteristics of the Ge(II) precursor determine whether the Ge(0) materials that result will be nanocrystals or nanowires.

摘要翻译： 提供用于合成Ge（0）纳米尺寸材料的路线的方法。 将Ge（II）前体溶解在加热至通常在约100℃至400℃的温度的配体中，足以将Ge（II）还原成Ge（0），其中配体是化合物 其可以结合到锗纳米材料的表面以随后防止纳米材料的团聚。 该配体包封Ge（O）材料的表面以防止附聚。 将所得溶液冷却用于处理，其中冷却特性可用于控制Ge（0）材料的尺寸和尺寸分布。 Ge（II）前体的特征决定了Ge（0）材料是纳米晶体还是纳米线。