公开(公告)号：US08026136B2

公开(公告)日：2011-09-27

申请号：US11964322

申请日：2007-12-26

申请人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8238 ,  H01L21/311

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.

摘要翻译： 存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

公开(公告)号：US20080157184A1

公开(公告)日：2008-07-03

申请号：US11649348

申请日：2007-01-03

申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513

摘要： A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

摘要翻译： 公开了一种通过向栅极施加足以使栅极向电荷存储层进行空穴隧道的正电压来操作存储单元的方法。 该方法应用于包括半导体层的存储单元，该半导体层具有设置在半导体层的表面下方并由沟道区分隔开的至少两个源极/漏极区域。 存储单元还具有设置在沟道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 设置在电荷存储层上方的上绝缘多层结构。 上绝缘多层结构包括下介电层和设置在下介电层上的上氮化物层，并且存储单元具有设置在上绝缘多层结构上方的栅极。

公开(公告)号：US07763935B2

公开(公告)日：2010-07-27

申请号：US11159269

申请日：2005-06-23

申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.

摘要翻译： 一种制造非易失性存储器件的方法至少包括以下步骤。 首先，提供形成有底部电介质层的基板。 然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。 该结构被热退火以推动间隔开的掺杂区域向外扩散。 退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。 最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

公开(公告)号：US07704865B2

公开(公告)日：2010-04-27

申请号：US11209875

申请日：2005-08-23

申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/425

CPC分类号： H01L21/2652 ,  H01L21/28211 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

摘要： Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.

摘要翻译： 在半导体存储器件中形成电荷俘获电介质层结构的方法包括：（a）提供半导体衬底; （b）在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）氧化氧化层; （e）在所述氧化物层上形成电荷捕获电介质层; 和（f）在电荷俘获电介质层上形成绝缘层; 以及包括：（a）提供半导体衬底的方法; （b）在干燥气氛中在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）在氧化物层上形成电荷俘获介电层; （e）在电荷捕获介电层上形成绝缘层; 和（f）在氢含量小于约0.01％的气氛中退火绝缘层。

公开(公告)号：US20060292800A1

公开(公告)日：2006-12-28

申请号：US11159269

申请日：2005-06-23

申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.

摘要翻译： 一种制造非易失性存储器件的方法至少包括以下步骤。 首先，提供形成有底部电介质层的基板。 然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。 该结构被热退火以推动间隔开的掺杂区域向外扩散。 退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。 最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

公开(公告)号：US20070108497A1

公开(公告)日：2007-05-17

申请号：US11274781

申请日：2005-11-15

申请人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Hsieh

发明人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Hsieh

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.

摘要翻译： 存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述衬底之间的界面的氢浓度小于约3×10 6， 11/2/2，以及用于形成这种记忆单元的方法。

公开(公告)号：US20070054449A1

公开(公告)日：2007-03-08

申请号：US11209875

申请日：2005-08-23

申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Hsieh

发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/28211 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

摘要： Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.

摘要翻译： 在半导体存储器件中形成电荷俘获电介质层结构的方法包括：（a）提供半导体衬底; （b）在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）氧化氧化层; （e）在所述氧化物层上形成电荷捕获电介质层; 和（f）在电荷俘获电介质层上形成绝缘层; 以及包括：（a）提供半导体衬底的方法; （b）在干燥气氛中在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）在氧化物层上形成电荷俘获介电层; （e）在电荷捕获介电层上形成绝缘层; 和（f）在氢含量小于约0.01％的气氛中退火绝缘层。

公开(公告)号：US20070166923A1

公开(公告)日：2007-07-19

申请号：US11334249

申请日：2006-01-18

申请人： Yen-Hao Shih ,  Shih-Chin Lee

发明人： Yen-Hao Shih ,  Shih-Chin Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954

摘要： A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon-nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.

摘要翻译： MOSFET制造工艺包括电介质硅界面的氮化，使得硅 - 悬挂键与氮原子连接，产生比硅 - 氢键更强的硅 - 氮键。 在基板上形成隧道电介质。 然后在隧道介电层上形成氮化物层。 然后将氮化物层的顶部转化为氧化物，并且衬底和隧道电介质之间的界面同时氮化氮化物层与氧化物的氮化。

公开(公告)号：US07053406B1

公开(公告)日：2006-05-30

申请号：US10907442

申请日：2005-04-01

申请人： ChiaHua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

发明人： ChiaHua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

IPC分类号： H01L29/72

CPC分类号： H01L27/1021 ,  H01L23/5252 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.

摘要翻译： 提供一次性可编程只读存储器。 顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。 第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。 具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。 导电层设置在P型半导体衬底上。 导电层还具有与第一P型掺杂层交叉的线性结构。 第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。 在导电层和第一N型掺杂层之间设置反熔丝层。

公开(公告)号：US07824991B2

公开(公告)日：2010-11-02

申请号：US11334249

申请日：2006-01-18

申请人： Yen-Hao Shih ,  Shih-Chin Lee

发明人： Yen-Hao Shih ,  Shih-Chin Lee

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954

摘要： A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.

摘要翻译： MOSFET制造工艺包括电介质硅界面的氮化，使得硅 - 悬挂键与氮原子连接，产生比硅 - 氢键更强的硅 - 氮键。 在基板上形成隧道电介质。 然后在隧道介电层上形成氮化物层。 然后将氮化物层的顶部转化为氧化物，并且衬底和隧道电介质之间的界面同时氮化氮化物层与氧化物的氮化。