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    One-time programmable read only memory and manufacturing method thereof
    1.
    发明授权
    One-time programmable read only memory and manufacturing method thereof 有权
    一次性可编程只读存储器及其制造方法

    公开(公告)号：US07053406B1

    公开(公告)日：2006-05-30

    申请号：US10907442

    申请日：2005-04-01

    申请人： ChiaHua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

    发明人： ChiaHua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

    IPC分类号： H01L29/72

    CPC分类号： H01L27/1021 ,  H01L23/5252 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.

    摘要翻译： 提供一次性可编程只读存储器。 顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。 第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。 具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。 导电层设置在P型半导体衬底上。 导电层还具有与第一P型掺杂层交叉的线性结构。 第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。 在导电层和第一N型掺杂层之间设置反熔丝层。

    Manufacturing method of one-time programmable read only memory
    2.
    发明授权
    Manufacturing method of one-time programmable read only memory 有权
    一次性可编程只读存储器的制造方法

    公开(公告)号：US07314815B2

    公开(公告)日：2008-01-01

    申请号：US11308550

    申请日：2006-04-06

    申请人： Chia-Hua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

    发明人： Chia-Hua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

    IPC分类号： H01L21/336 ,  H01L21/326 ,  H01L21/479 ,  H01L21/44

    CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L27/1021

    摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.

    摘要翻译： 提供一次性可编程只读存储器。 顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。 第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。 具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。 导电层设置在P型半导体衬底上。 导电层还具有与第一P型掺杂层交叉的线性结构。 第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。 在导电层和第一N型掺杂层之间设置反熔丝层。

    MANUFACTURING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY
    3.
    发明申请
    MANUFACTURING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY 有权
    一次性编程只读存储器的制造方法

    公开(公告)号：US20060199361A1

    公开(公告)日：2006-09-07

    申请号：US11308550

    申请日：2006-04-06

    申请人： Chia-Hua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

    发明人： Chia-Hua Ho ,  Yen-Hao Shih ,  Hsiang-Lan Lung ,  Shih-Ping Hong ,  Shih-Chin Lee

    IPC分类号： G11C17/00 ,  H01L21/44

    CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L27/1021

    摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.

    摘要翻译： 提供一次性可编程只读存储器。 顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。 第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。 具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。 导电层设置在P型半导体衬底上。 导电层还具有与第一P型掺杂层交叉的线性结构。 第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。 在导电层和第一N型掺杂层之间设置反熔丝层。

    3D two bit-per-cell NAND flash memory
    4.
    发明授权
    3D two bit-per-cell NAND flash memory 有权
    3D双比特单元NAND闪存

    公开(公告)号：US08437192B2

    公开(公告)日：2013-05-07

    申请号：US12785291

    申请日：2010-05-21

    申请人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

    发明人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

    IPC分类号： G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C5/02 ,  G11C5/06

    CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

    摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

    COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS
    5.
    发明申请
    COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS 有权
    用于形成相变材料的复合靶材溅射

    公开(公告)号：US20120193595A1

    公开(公告)日：2012-08-02

    申请号：US13076169

    申请日：2011-03-30

    申请人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

    发明人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

    IPC分类号： H01L45/00 ,  C23C14/14 ,  C23C14/34

    CPC分类号： H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

    摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

    摘要翻译： 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

    Composite target sputtering for forming doped phase change materials
    6.
    发明授权
    Composite target sputtering for forming doped phase change materials 有权
    用于形成掺杂相变材料的复合靶溅射

    公开(公告)号：US08426242B2

    公开(公告)日：2013-04-23

    申请号：US13076169

    申请日：2011-03-30

    申请人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

    发明人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

    IPC分类号： H01L21/06

    CPC分类号： H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

    摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

    摘要翻译： 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

    Memory device and method for sensing and fixing margin cells
    7.
    发明授权
    Memory device and method for sensing and fixing margin cells 有权
    用于检测和固定边缘细胞的记忆装置和方法

    公开(公告)号：US08406033B2

    公开(公告)日：2013-03-26

    申请号：US12488995

    申请日：2009-06-22

    申请人： Hsiang-Lan Lung ,  Yen-Hao Shih

    发明人： Hsiang-Lan Lung ,  Yen-Hao Shih

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

    摘要： A programmable resistance memory device with a margin cell detection and refresh resources. Margin cell detection and refresh can include reading a selected cell, measuring a time interval which correlates with resistance of the selected cell during said reading, and enabling a refresh process if the measured time falls within a pre-specified range. The refresh process includes determining a data value stored in the selected cell, using for example a destructive read process, and refreshing the data value in the selected cell. The time interval can be measured by detecting timing within the sensing interval of a transition of voltage or current on a bit line across a threshold.

    摘要翻译： 具有边缘单元检测和刷新资源的可编程电阻存储器件。 边缘细胞检测和刷新可以包括读取所选择的细胞，测量与所述读取期间所选细胞的电阻相关的时间间隔，以及如果测量的时间落在预定范围内，则启用刷新过程。 刷新过程包括使用例如破坏性读取处理确定存储在所选择的单元中的数据值，以及刷新所选择的单元中的数据值。 可以通过检测跨越阈值的位线上的电压或电流的转变的感测间隔内的定时来测量时间间隔。

    PHASE CHANGE MEMORY CODING
    10.
    发明申请
    PHASE CHANGE MEMORY CODING 有权
    相变存储器编码

    公开(公告)号：US20110317480A1

    公开(公告)日：2011-12-29

    申请号：US12823508

    申请日：2010-06-25

    申请人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    发明人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    IPC分类号： G11C11/00 ,  H01L21/06

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

    摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

    摘要翻译： 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。