公开(公告)号：US07704865B2

公开(公告)日：2010-04-27

申请号：US11209875

申请日：2005-08-23

申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/425

CPC分类号： H01L21/2652 ,  H01L21/28211 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

摘要： Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.

摘要翻译： 在半导体存储器件中形成电荷俘获电介质层结构的方法包括：（a）提供半导体衬底; （b）在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）氧化氧化层; （e）在所述氧化物层上形成电荷捕获电介质层; 和（f）在电荷俘获电介质层上形成绝缘层; 以及包括：（a）提供半导体衬底的方法; （b）在干燥气氛中在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）在氧化物层上形成电荷俘获介电层; （e）在电荷捕获介电层上形成绝缘层; 和（f）在氢含量小于约0.01％的气氛中退火绝缘层。

公开(公告)号：US08026136B2

公开(公告)日：2011-09-27

申请号：US11964322

申请日：2007-12-26

申请人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8238 ,  H01L21/311

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.

摘要翻译： 存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

公开(公告)号：US08022465B2

公开(公告)日：2011-09-20

申请号：US11274781

申请日：2005-11-15

申请人： Yen-Hao Shih ,  Min-Ta Wu ,  Shin-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Min-Ta Wu ,  Shin-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.

摘要翻译： 存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

公开(公告)号：US20070037328A1

公开(公告)日：2007-02-15

申请号：US11203087

申请日：2005-08-15

申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

公开(公告)号：US07560762B2

公开(公告)日：2009-07-14

申请号：US11209437

申请日：2005-08-23

申请人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/80

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

摘要： A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

摘要翻译： NAND型闪存器件包括覆盖相应字线的非对称浮动栅极。 给定的浮动栅极被充分地耦合到其相应的字线，使得大的栅极（即，字线）偏置电压将使浮动栅极与可以反转浮动栅极下方的沟道的电压耦合。 因此，浮置栅极下的反相通道可以作为源极/漏极。 结果，存储器件不需要浅结或辅助栅。 此外，存储器件具有相对较低的浮置栅极至浮置栅极（FG-FG）干扰。

公开(公告)号：US08846549B2

公开(公告)日：2014-09-30

申请号：US11235786

申请日：2005-09-27

申请人： Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/31 ,  G11C16/04 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513

摘要： A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm−3 and an interface trap density of up to 5E11 cm−2 eV−1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.

摘要翻译： 半导体衬底上的非易失性存储器件可以包括衬底上的底部氧化物层，底部氧化物层上的中间氮化硅层和中间层上的顶部氧化物层。 底部氧化物层可以具有高达5E19cm-3的氢浓度和高达5E11cm-2eV-1的界面陷阱密度。 三层结构可以是用于存储器件的电荷捕获结构，并且存储器件还可以包括在结构上的栅极和衬底中的源极和漏极区域。

公开(公告)号：US07977227B2

公开(公告)日：2011-07-12

申请号：US12216679

申请日：2008-07-09

申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115

摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

公开(公告)号：US07414282B2

公开(公告)日：2008-08-19

申请号：US11203087

申请日：2005-08-15

申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

公开(公告)号：US20090075466A1

公开(公告)日：2009-03-19

申请号：US12216679

申请日：2008-07-09

申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/3205

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115

摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

公开(公告)号：US09018615B2

公开(公告)日：2015-04-28

申请号：US11833563

申请日：2007-08-03

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00 ,  H01L45/00

CPC分类号： H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144

摘要： A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.

摘要翻译： 包括能够通过施加能量在电性能状态之间切换的存储材料的存储单元装置包括第一和第二电极，与第二电极电接触的存储材料（例如相变材料）插头 以及由电介质形式支撑并与第一电极和记忆材料塞电接触的导电膜。 电介质形式在第一电极附近较宽，在相变插头附近较窄。 导电膜与相变插塞的接触面积部分地由形成导电膜的电介质形状的几何形状限定。 此外，制造该器件的方法包括在第一电极上构建电介质形式，以及在电介质形式上形成导电膜的步骤。