公开(公告)号：US06514807B1

公开(公告)日：2003-02-04

申请号：US09955779

申请日：2001-09-18

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Hung-Sui Lin ,  Shih-Keng Cho ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Hung-Sui Lin ,  Shih-Keng Cho ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11293 ,  H01L27/105

摘要： The present invention provides a method for fabricating a semiconductor device that can be applied in system on chip (SOC), comprising: providing a substrate with a memory cell region and a peripheral circuit region; forming a plurality of bit-lines in the memory cell region; forming a first and a second dielectric layers respectively in the memory cell region and the peripheral circuit region; and forming a plurality of gates. Next, a blanket ion implantation step is performed to form a plurality of P type LDDs in the substrate besides the gates in a PMOS device region within the peripheral circuit region, without forming an anti-punch through region in the substrate of the memory cell region. Afterwards, a plurality of spacers are formed, connected to one another. An ion implantation step is performed to form a plurality of P type source/drain regions.

摘要翻译： 本发明提供一种可应用于片上系统（SOC）的半导体器件的制造方法，包括：向衬底提供存储单元区域和外围电路区域; 在所述存储单元区域中形成多个位线; 在所述存储单元区域和所述外围电路区域中分别形成第一和第二电介质层; 并形成多个门。 接下来，进行覆盖离子注入步骤，以在外围电路区域中的PMOS器件区域中的栅极之外的衬底中形成多个P型LDD，而不在存储单元区域的衬底中形成抗穿通区域 。 之后，形成多个间隔件，彼此连接。 执行离子注入步骤以形成多个P型源极/漏极区域。

公开(公告)号：US06790730B2

公开(公告)日：2004-09-14

申请号：US10156325

申请日：2002-05-24

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11253 ,  H01L21/26586 ,  H01L27/112

摘要： A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

摘要翻译： 描述了一种用于掩模只读存储器件的制造方法。 该方法提供衬底，并且在衬底上形成掺杂导电层。 之后，将掺杂的导电层图案化以形成多个棒状掺杂导电层，随后通过热氧化在基板上和棒状导电层上形成电介质层。 多个扩散区同时形成在基板中的棒状导电层的下方。 在电介质层上进一步形成图案化的导电层。

公开(公告)号：US06706575B2

公开(公告)日：2004-03-16

申请号：US10055265

申请日：2002-01-22

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/115

摘要： A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.

摘要翻译： 描述了制造非易失性存储器的方法。 提供其上具有条带堆叠结构的基板。 然后在衬底旁边的衬底上形成掩埋漏极，并在掩埋漏极上形成绝缘层。 在衬底上顺序形成硅层和覆盖层。 然后，在垂直于埋地漏极的方向上连续地对盖层，硅层和条带堆叠结构进行图案化，其中条带层叠结构被图案化成多个栅极。 衬底氧化物层形成在栅极，衬底和硅层的暴露表面上。 此后，除去盖层，并在硅层的暴露表面上形成金属硅化物层。

公开(公告)号：US07002849B2

公开(公告)日：2006-02-21

申请号：US10983019

申请日：2004-11-05

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C5/06 ,  G06F12/00

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14

摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

公开(公告)号：US20050082597A1

公开(公告)日：2005-04-21

申请号：US10983019

申请日：2004-11-05

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14

摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

摘要翻译： 描述了用氮化物隧穿层编程和擦除非易失性存储器的方法。 非易失性存储器通过向栅极施加第一电压并使衬底接地以接通源极和漏极之间的沟道并且向漏极施加第二电压并且将源接地以感应通道中的电流来编程 从而在其中产生热电子。 热电子通过氮化物隧穿层注入到非挥发性的电荷捕获层中并被捕获在其中。 通过向漏极施加第一正偏压，向栅极施加第二正偏压，并且将源极和衬底接地以在沟道区域中产生热电子空穴来擦除非易失性存储器。 热电子空穴通过氮化物隧穿层注入电荷捕获层。

公开(公告)号：US06709921B2

公开(公告)日：2004-03-23

申请号：US09967717

申请日：2001-09-27

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

摘要翻译： 描述了具有分离浮动栅极的闪速存储器件的制造方法。 该方法提供了一种衬底，其中氧化物层和图案化的牺牲层依次形成在衬底上。 然后使用图案化的牺牲层作为掩模，进行离子注入，以在图案化牺牲层的侧面旁边的衬底中形成具有轻掺杂的源/漏区的源/漏区。 进一步进行各向同性蚀刻以去除图案化牺牲层的一部分，然后在图案化牺牲层的侧壁上形成两个导电间隔物。 然后去除由两个导电间隔物暴露的图案化牺牲层和氧化物层以形成两个浮动栅极。 随后，在基板上形成电介质层和控制栅极。

公开(公告)号：US06919607B2

公开(公告)日：2005-07-19

申请号：US10142697

申请日：2002-05-08

申请人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/78

CPC分类号： H01L27/11253 ,  H01L27/112 ,  H01L27/11266

摘要： A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

摘要翻译： 提供2位掩模ROM器件的结构及其制造方法。 存储器结构包括衬底，栅极结构，2位编码注入区，间隔区，埋漏区，隔离结构和字线。 栅极结构设置在衬底上，而编码注入区域位于栅极结构侧面的衬底中。 此外，至少一个间隔物布置在栅极结构的侧面旁边，并且掩埋漏极区域设置在衬垫旁边的衬垫旁边。 此外，掩埋漏极区域和编码注入区域还包括其间的缓冲区域。 此外，绝缘结构布置在衬底上方，在掩埋漏极区域之上，而字留置被设置在栅极结构上。

公开(公告)号：US06649971B1

公开(公告)日：2003-11-18

申请号：US10064905

申请日：2002-08-28

申请人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L29788

CPC分类号： H01L29/7923

摘要： A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.

摘要翻译： 描述了用于降低第二位效应的NROM单元。 本发明的NORM单元由衬底，设置在衬底上的氧化硅/氮化硅/氧化硅（ONO）层，设置在氧化硅/氮化硅/氧化硅层上的栅极，源/漏区 配置在栅极旁边的衬底中，以及配置在源极/漏极区域和栅极旁边的ONO层之间的浅阱掺杂区域。 浅阱掺杂区域的深度足够小，以防止对流向源极/漏极区域的电流的干扰。

公开(公告)号：US06531361B1

公开(公告)日：2003-03-11

申请号：US10142720

申请日：2002-05-08

申请人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： A fabrication method for a memory device is described. The method includes sequentially forming a pad oxide layer and a mask layer on a substrate, wherein the mask layer exposes a portion of the pad oxide layer. Thereafter, an ion implantation process is conducted to form a buried bit line in the substrate that is not covered by the mask layer. A raised bit line is then formed on the pad oxide layer above the buried bit line. The mask layer and the pad oxide layer are then removed, followed by forming a conformal gate oxide layer on the surface of the substrate and the raised bit line. A word line is further formed on the gate oxide layer.

摘要翻译： 描述了一种用于存储器件的制造方法。 该方法包括在衬底上顺序地形成衬垫氧化物层和掩模层，其中掩模层暴露衬垫氧化物层的一部分。 此后，进行离子注入工艺以在衬底中形成未被掩模层覆盖的掩埋位线。 然后在掩埋位线上方的焊盘氧化物层上形成隆起的位线。 然后去除掩模层和焊盘氧化物层，随后在衬底的表面和凸起的位线上形成共形栅极氧化物层。 在栅极氧化层上进一步形成字线。

公开(公告)号：US06587387B1

公开(公告)日：2003-07-01

申请号：US10055571

申请日：2002-01-22

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C2900

CPC分类号： G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C2029/5006

摘要： A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each buried bit-line has two end portions with a combined length of about 3˜30 &mgr;m and can have an N-type conductivity or a P-type conductivity.

摘要翻译： 描述了面罩ROM测试装置。 掩模ROM测试装置包括衬底，衬底中的多个掩埋位线和垂直于掩埋位线的衬底上的多个字线。 每个埋置的位线具有两个具有约3〜30μm的组合长度的端部，并且可以具有N型导电性或P型导电性。