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    Method to fabricate aligned dual damascene openings
    1.
    发明授权
    Method to fabricate aligned dual damascene openings 有权
    制造对准双镶嵌开口的方法

    公开(公告)号：US07372156B2

    公开(公告)日：2008-05-13

    申请号：US11174805

    申请日：2005-07-05

    申请人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    发明人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    IPC分类号： H01L29/40

    CPC分类号： H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

    摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

    摘要翻译： 对准的双镶嵌开口结构，包括以下。 具有形成在其上的金属结构的结构。 金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。 在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。 下通道开口与上沟槽开口连通。 其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

    Method to fabricate aligned dual damascene openings
    2.
    发明授权
    Method to fabricate aligned dual damascene openings 有权
    制造对准双镶嵌开口的方法

    公开(公告)号：US06967156B2

    公开(公告)日：2005-11-22

    申请号：US10690998

    申请日：2003-10-22

    申请人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    发明人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L29/06

    CPC分类号： H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

    摘要： A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. Simultaneously patterning the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening.

    摘要翻译： 一种形成对准的双镶嵌开口的方法，包括以下顺序步骤。 在金属结构上形成层叠。 层叠层按升序包括底蚀刻停止层; 下介电材料层; 中间蚀刻停止层; 中间介电材料层; 和上介电层。 图案化的掩模层形成在图案化的上介电层上，留下图案化的上介电层的暴露的相对部分。 使用图案化掩模层和上介电层的暴露部分作为掩模，将中介电材料层图案化以形成开口。 使用图案化的上电介质层作为掩模，同时对图案化的中间介电材料层进行图案化以形成初始上沟槽开口; 并且使用图案化掩模层和图案化的中间蚀刻停止层作为掩模的下部电介质材料层形成与前述上部沟槽开口对准的开口下部通孔。

    Integrated circuit with simultaneous fabrication of dual damascene via and trench
    6.
    发明授权
    Integrated circuit with simultaneous fabrication of dual damascene via and trench 有权
    集成电路，同时制造双镶嵌通孔和沟槽

    公开(公告)号：US06995087B2

    公开(公告)日：2006-02-07

    申请号：US10328512

    申请日：2002-12-23

    申请人： Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

    发明人： Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76811 ,  H01L21/76813

    摘要： An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.

    摘要翻译： 集成电路制造方法包括提供基底，形成第一导体，形成第一阻挡层，形成第一介电层，形成掩模层。 该方法还包括在掩模层中形成第一通孔，在掩模层中形成第一沟槽开口，同时在掩模层下方的层中形成第二通孔，并形成穿过掩模层的第二沟槽开口， 在掩模层下面的层中并且同时在掩模层下方的另一层中形成第三通孔。 该方法还包括使用第三通孔开口和掩模层去除第一阻挡层以形成沟槽和通孔，以及用导体填充沟槽和通孔以形成与第一导体接触的沟槽和通孔导体。

    Method to fabricate aligned dual damacene openings
    7.
    发明申请
    Method to fabricate aligned dual damacene openings 有权
    制造对齐双重断裂孔的方法

    公开(公告)号：US20060003573A1

    公开(公告)日：2006-01-05

    申请号：US11174805

    申请日：2005-07-05

    申请人： Yeow Lim ,  Wuping Liu ,  Tae Lee ,  Bei Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Neo

    发明人： Yeow Lim ,  Wuping Liu ,  Tae Lee ,  Bei Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Neo

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

    摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

    摘要翻译： 对准的双镶嵌开口结构，包括以下。 具有形成在其上的金属结构的结构。 金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。 在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。 下通道开口与上沟槽开口连通。 其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

    Crack-arresting structure for through-silicon vias
    8.
    发明授权
    Crack-arresting structure for through-silicon vias 有权
    通硅通孔的破裂结构

    公开(公告)号：US08860185B2

    公开(公告)日：2014-10-14

    申请号：US13357960

    申请日：2012-01-25

    申请人： Shaoning Yuan ,  Yue Kang Lu ,  Yeow Kheng Lim ,  Juan Boon Tan

    发明人： Shaoning Yuan ,  Yue Kang Lu ,  Yeow Kheng Lim ,  Juan Boon Tan

    IPC分类号： H01L23/544

    CPC分类号： H01L23/585 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/014

    摘要： The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure.

    摘要翻译： 本文公开的主题涉及形成在半导体芯片上的结构，其用于至少部分地解决半导体芯片中可能由于存在穿硅通孔（TSV）而导致的热诱导应力和金属化系统开裂问题，以及 这可能主要是由于TSV的材料与通常构成半导体芯片的其余部分的半导体材料之间的热膨胀的显着差异。 本文公开的一种装置包括基底和位于基底上方的裂缝阻止结构，所述裂缝阻止结构包括多个裂缝阻止元件，并且当从上方观察时具有周边。 该装置还包括至少部分地位于裂缝阻止结构的周边内的导电结构，以及延伸穿过裂缝阻止结构中的开口的导电元件，其中导电元件与导电结构导电耦合。