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公开(公告)号：US20060286730A1
公开(公告)日：2006-12-21
申请号：US11154377
申请日：2005-06-15
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over a sidewall of the gate. Then, a source/drain trench is formed in the substrate at two sides of the gate respectively. Next, an outermost offspacer of the offspacers is removed to expose a flat surface on a surface of the substrate. Thereafter, the source/drain trenches are filled to form a source/drain region. Then, a lightly doped drain (LDD) region is formed in a portion of the substrate under the flat surface.
摘要翻译： 提供半导体结构和形成半导体结构的方法。 本发明的半导体结构的形成方法可以包括以下步骤。 首先，提供衬底，其中在衬底上形成栅极，并且在栅极的侧壁上方形成多个脱离层。 然后，在栅极的两侧分别在衬底中形成源极/漏极沟槽。 接下来，除去离子的最外层的隔离物以露出基底表面上的平坦表面。 此后，填充源极/漏极沟槽以形成源极/漏极区域。 然后，在平坦表面下的基板的一部分中形成轻掺杂漏极（LDD）区域。
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公开(公告)号：US07186657B2
公开(公告)日：2007-03-06
申请号：US11160629
申请日：2005-06-30
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31111 , H01L21/31122 , H01L21/823462 , H01L21/823481 , H01L29/517 , H01L29/78 , Y10S438/906
摘要： A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.
摘要翻译： 晶片具有沟槽，形成在沟槽中的STI层，覆盖晶片和STI层的含HfO 2的栅极电介质，形成在含HfO 2的栅极电介质上的栅电极和至少形成在栅电极旁边的间隔物 。 将晶片预热，并提供富含溴的气体等离子体以去除部分含HfO 2的栅极电介质。
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公开(公告)号：US20060099763A1
公开(公告)日：2006-05-11
申请号：US10904210
申请日：2004-10-28
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.
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公开(公告)号：US06853031B2
公开(公告)日：2005-02-08
申请号：US10417167
申请日：2003-04-17
申请人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66787 , H01L29/0657 , H01L29/1037 , H01L29/42376
摘要： A structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET) includes a plurality of trapezoid pillars being transversely formed on an crystalline substrate or Silicon-On-Insulator (SOI) wafer. The trapezoid pillars can juxtapose with both ends connected each other. Each trapezoid pillar has a source, a channel region, and a drain aligned in longitudinal direction and a gate latitudinally superposes the channel region of the trapezoid pillar. The triple gate field effect transistor comprises a dielectric layer formed between the channel region and the conductive gate structure.
摘要翻译： 梯形三栅场效应晶体管（FET）的结构包括在晶体衬底或绝缘体上硅晶片上横向形成的多个梯形柱。 梯形柱可以并置，两端相互连接。 每个梯形柱具有在纵向方向上排列的源极，沟道区和漏极，栅极横向叠加梯形柱的沟道区域。 三栅场效应晶体管包括形成在沟道区和导电栅结构之间的电介质层。
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公开(公告)号：US07326622B2
公开(公告)日：2008-02-05
申请号：US11164031
申请日：2005-11-08
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.
摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。
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公开(公告)号：US20060094195A1
公开(公告)日：2006-05-04
申请号：US11164031
申请日：2005-11-08
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.
摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。
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公开(公告)号：US20060019452A1
公开(公告)日：2006-01-26
申请号：US11160629
申请日：2005-06-30
IPC分类号： H01L21/336
CPC分类号： H01L21/31116 , H01L21/31111 , H01L21/31122 , H01L21/823462 , H01L21/823481 , H01L29/517 , H01L29/78 , Y10S438/906
摘要： A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.
摘要翻译： 晶片具有沟槽，形成在沟槽中的STI层，覆盖晶片和STI层的含HfO 2的栅极电介质，形成在含HfO 2的栅极电介质上的栅电极和至少形成在栅电极旁边的间隔物 。 将晶片预热，并提供富含溴的气体等离子体以去除部分含HfO 2的栅极电介质。
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公开(公告)号：US20060019451A1
公开(公告)日：2006-01-26
申请号：US10710581
申请日：2004-07-22
IPC分类号： H01L21/461
CPC分类号： H01L21/31116 , H01L21/31111 , H01L21/31122 , H01L21/823462 , H01L21/823481 , H01L29/517 , H01L29/78 , Y10S438/906
摘要： A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.
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公开(公告)号：US20070117304A1
公开(公告)日：2007-05-24
申请号：US11624703
申请日：2007-01-19
IPC分类号： H01L21/8238 , H01L21/31
CPC分类号： H01L21/31116 , H01L21/31111 , H01L21/31122 , H01L21/823462 , H01L21/823481 , H01L29/517 , H01L29/78 , Y10S438/906
摘要： A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. An ion bombardment utilizing Ar, He, O2, CHF3 or mixture thereof is performed to convert the exposed HfO2-containing gate dielectric to an intergraded layer, and a wet chemical is utilized to remove the intergraded layer.
摘要翻译： 晶片具有沟槽，形成在沟槽中的STI层，覆盖晶片和STI层的含HfO 2的栅极电介质，形成在含HfO 2的栅极电介质上的栅电极和至少形成在栅电极旁边的间隔物 。 进行利用Ar，He，O 2，CHF 3或其混合物的离子轰击，以将暴露的含HfO 2的栅极电介质转化为层间化合物，并使用湿化学品去除层间化合物。
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公开(公告)号：US20070090491A1
公开(公告)日：2007-04-26
申请号：US11583139
申请日：2006-10-19
申请人： Jiunn-Ren Hwang , Wei-Tsun Shiau
发明人： Jiunn-Ren Hwang , Wei-Tsun Shiau
IPC分类号： H01L29/04
CPC分类号： H01L21/76254 , H01L21/2007 , H01L29/045
摘要： A semiconductor structure with silicon on insulator is disclosed in this present invention. The semiconductor structure at least comprises a first substrate and a second substrate. The crystal orientation of the first substrate is in a first orientation favorable for dicing the semiconductor structure into chips, and the crystal orientation of the second substrate is in a second crystal orientation favorable to the electron carrier mobility. Hence, this invention can efficiently improve the yield of the semiconductor device by reducing the fracture during dicing. Additionally, this invention can improve the performance of the semiconductor device by raising the electron mobility in the substrate.
摘要翻译： 在本发明中公开了具有绝缘体硅的半导体结构。 半导体结构至少包括第一基板和第二基板。 第一衬底的晶体取向为有利于将半导体结构切割成芯片的第一取向，并且第二衬底的晶体取向为有利于电子载流子迁移率的第二晶体取向。 因此，本发明可以通过减少切割时的断裂而有效地提高半导体器件的产量。 此外，本发明可以通过提高衬底中的电子迁移率来改善半导体器件的性能。
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